| 1 |
49 |
qaztronic |
# -------------------------------------------------------------------------- #
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| 2 |
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#
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| 3 |
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#
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| 4 |
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# -------------------------------------------------------------------------- #
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| 5 |
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| 6 |
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set_global_assignment -name FAMILY "Arria 10"
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| 7 |
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set_global_assignment -name DEVICE 10AX115S2F45I1SG
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| 8 |
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set_global_assignment -name TOP_LEVEL_ENTITY a10gx_riffa_top
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| 9 |
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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| 10 |
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| 11 |
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# -------------------------------------------------------------------------- #
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| 12 |
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set_location_assignment PIN_AU33 -to clk_50
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| 13 |
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| 14 |
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set_location_assignment PIN_BD27 -to cpu_resetn
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| 15 |
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set_location_assignment PIN_L28 -to user_led_g[0]
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| 16 |
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set_location_assignment PIN_K26 -to user_led_g[1]
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| 17 |
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set_location_assignment PIN_K25 -to user_led_g[2]
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| 18 |
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set_location_assignment PIN_L25 -to user_led_g[3]
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| 19 |
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set_location_assignment PIN_J24 -to user_led_g[4]
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| 20 |
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set_location_assignment PIN_A19 -to user_led_g[5]
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| 21 |
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set_location_assignment PIN_C18 -to user_led_g[6]
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| 22 |
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set_location_assignment PIN_D18 -to user_led_g[7]
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| 23 |
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set_location_assignment PIN_L27 -to user_led_r[0]
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| 24 |
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set_location_assignment PIN_J26 -to user_led_r[1]
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| 25 |
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set_location_assignment PIN_K24 -to user_led_r[2]
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| 26 |
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set_location_assignment PIN_L23 -to user_led_r[3]
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| 27 |
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set_location_assignment PIN_B20 -to user_led_r[4]
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| 28 |
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set_location_assignment PIN_C19 -to user_led_r[5]
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| 29 |
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set_location_assignment PIN_D19 -to user_led_r[6]
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| 30 |
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set_location_assignment PIN_M23 -to user_led_r[7]
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| 31 |
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| 32 |
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| 33 |
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| 34 |
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set_location_assignment PIN_T12 -to user_pb[0]
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| 35 |
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set_location_assignment PIN_U12 -to user_pb[1]
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| 36 |
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set_location_assignment PIN_U11 -to user_pb[2]
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| 37 |
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| 38 |
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| 39 |
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| 40 |
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# -------------------------------------------------------------------------- #
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| 41 |
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# PCIe
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| 42 |
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set_location_assignment PIN_BC30 -to pcie_perstn
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| 43 |
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| 44 |
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set_location_assignment PIN_AT40 -to pcie_rx_p[0]
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| 45 |
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set_location_assignment PIN_AP40 -to pcie_rx_p[1]
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| 46 |
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set_location_assignment PIN_AN42 -to pcie_rx_p[2]
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| 47 |
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set_location_assignment PIN_AM40 -to pcie_rx_p[3]
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| 48 |
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set_location_assignment PIN_AL42 -to pcie_rx_p[4]
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| 49 |
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set_location_assignment PIN_AK40 -to pcie_rx_p[5]
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| 50 |
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set_location_assignment PIN_AJ42 -to pcie_rx_p[6]
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| 51 |
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set_location_assignment PIN_AH40 -to pcie_rx_p[7]
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| 52 |
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| 53 |
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set_location_assignment PIN_BB44 -to pcie_tx_p[0]
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| 54 |
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set_location_assignment PIN_BA42 -to pcie_tx_p[1]
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| 55 |
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set_location_assignment PIN_AY44 -to pcie_tx_p[2]
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| 56 |
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set_location_assignment PIN_AW42 -to pcie_tx_p[3]
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| 57 |
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set_location_assignment PIN_AV44 -to pcie_tx_p[4]
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| 58 |
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set_location_assignment PIN_AU42 -to pcie_tx_p[5]
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| 59 |
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set_location_assignment PIN_AT44 -to pcie_tx_p[6]
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| 60 |
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set_location_assignment PIN_AR42 -to pcie_tx_p[7]
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| 61 |
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| 62 |
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| 63 |
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set_location_assignment PIN_AL37 -to pcie_edge_refclk_p
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| 64 |
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| 65 |
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| 66 |
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# -------------------------------------------------------------------------- #
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| 67 |
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#Group0
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| 68 |
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set_location_assignment PIN_B28 -to emif_0_mem_mem_dq[0]
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| 69 |
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set_location_assignment PIN_A28 -to emif_0_mem_mem_dq[1]
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| 70 |
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set_location_assignment PIN_A27 -to emif_0_mem_mem_dq[2]
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| 71 |
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set_location_assignment PIN_B27 -to emif_0_mem_mem_dq[3]
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| 72 |
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set_location_assignment PIN_D27 -to emif_0_mem_mem_dq[4]
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| 73 |
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set_location_assignment PIN_E27 -to emif_0_mem_mem_dq[5]
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| 74 |
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set_location_assignment PIN_D26 -to emif_0_mem_mem_dq[6]
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| 75 |
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set_location_assignment PIN_D28 -to emif_0_mem_mem_dq[7]
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| 76 |
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| 77 |
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set_location_assignment PIN_B26 -to emif_0_mem_mem_dqs[0]
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| 78 |
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set_location_assignment PIN_C26 -to emif_0_mem_mem_dqs_n[0]
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| 79 |
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| 80 |
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set_location_assignment PIN_E26 -to emif_0_mem_mem_dbi_n[0]
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| 81 |
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| 82 |
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| 83 |
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#Group1
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| 84 |
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set_location_assignment PIN_G25 -to emif_0_mem_mem_dq[8]
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| 85 |
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set_location_assignment PIN_H25 -to emif_0_mem_mem_dq[9]
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| 86 |
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set_location_assignment PIN_G26 -to emif_0_mem_mem_dq[10]
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| 87 |
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set_location_assignment PIN_H26 -to emif_0_mem_mem_dq[11]
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| 88 |
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set_location_assignment PIN_G28 -to emif_0_mem_mem_dq[12]
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| 89 |
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set_location_assignment PIN_F27 -to emif_0_mem_mem_dq[13]
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| 90 |
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set_location_assignment PIN_K27 -to emif_0_mem_mem_dq[14]
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| 91 |
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set_location_assignment PIN_F28 -to emif_0_mem_mem_dq[15]
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| 92 |
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| 93 |
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set_location_assignment PIN_H28 -to emif_0_mem_mem_dqs[1]
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| 94 |
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set_location_assignment PIN_J27 -to emif_0_mem_mem_dqs_n[1]
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| 95 |
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| 96 |
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set_location_assignment PIN_G27 -to emif_0_mem_mem_dbi_n[1]
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| 97 |
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| 98 |
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| 99 |
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#Group 2
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| 100 |
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set_location_assignment PIN_D31 -to emif_0_mem_mem_dq[16]
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| 101 |
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set_location_assignment PIN_E31 -to emif_0_mem_mem_dq[17]
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| 102 |
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set_location_assignment PIN_B31 -to emif_0_mem_mem_dq[18]
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| 103 |
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set_location_assignment PIN_C31 -to emif_0_mem_mem_dq[19]
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| 104 |
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set_location_assignment PIN_A30 -to emif_0_mem_mem_dq[20]
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| 105 |
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set_location_assignment PIN_E30 -to emif_0_mem_mem_dq[21]
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| 106 |
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set_location_assignment PIN_B30 -to emif_0_mem_mem_dq[22]
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| 107 |
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set_location_assignment PIN_D29 -to emif_0_mem_mem_dq[23]
|
| 108 |
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| 109 |
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set_location_assignment PIN_C30 -to emif_0_mem_mem_dqs[2]
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| 110 |
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set_location_assignment PIN_C29 -to emif_0_mem_mem_dqs_n[2]
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| 111 |
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| 112 |
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set_location_assignment PIN_A29 -to emif_0_mem_mem_dbi_n[2]
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| 113 |
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| 114 |
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#Group 3
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| 115 |
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set_location_assignment PIN_K30 -to emif_0_mem_mem_dq[24]
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| 116 |
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set_location_assignment PIN_H30 -to emif_0_mem_mem_dq[25]
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| 117 |
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set_location_assignment PIN_G30 -to emif_0_mem_mem_dq[26]
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| 118 |
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set_location_assignment PIN_K31 -to emif_0_mem_mem_dq[27]
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| 119 |
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set_location_assignment PIN_H29 -to emif_0_mem_mem_dq[28]
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| 120 |
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set_location_assignment PIN_K29 -to emif_0_mem_mem_dq[29]
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| 121 |
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set_location_assignment PIN_J29 -to emif_0_mem_mem_dq[30]
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| 122 |
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set_location_assignment PIN_F29 -to emif_0_mem_mem_dq[31]
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| 123 |
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| 124 |
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set_location_assignment PIN_L30 -to emif_0_mem_mem_dqs[3]
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| 125 |
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set_location_assignment PIN_L29 -to emif_0_mem_mem_dqs_n[3]
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| 126 |
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| 127 |
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set_location_assignment PIN_F30 -to emif_0_mem_mem_dbi_n[3]
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| 128 |
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| 129 |
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#Group 4
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| 130 |
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set_location_assignment PIN_AC31 -to emif_0_mem_mem_dq[32]
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| 131 |
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set_location_assignment PIN_AB31 -to emif_0_mem_mem_dq[33]
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| 132 |
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set_location_assignment PIN_W31 -to emif_0_mem_mem_dq[34]
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| 133 |
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set_location_assignment PIN_Y31 -to emif_0_mem_mem_dq[35]
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| 134 |
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set_location_assignment PIN_AD31 -to emif_0_mem_mem_dq[36]
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| 135 |
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set_location_assignment PIN_AD32 -to emif_0_mem_mem_dq[37]
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| 136 |
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set_location_assignment PIN_AD33 -to emif_0_mem_mem_dq[38]
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| 137 |
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set_location_assignment PIN_AA30 -to emif_0_mem_mem_dq[39]
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| 138 |
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| 139 |
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set_location_assignment PIN_Y32 -to emif_0_mem_mem_dqs[4]
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| 140 |
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set_location_assignment PIN_AA32 -to emif_0_mem_mem_dqs_n[4]
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| 141 |
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| 142 |
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set_location_assignment PIN_AB32 -to emif_0_mem_mem_dbi_n[4]
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| 143 |
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| 144 |
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#Group 5
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| 145 |
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set_location_assignment PIN_AE31 -to emif_0_mem_mem_dq[40]
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| 146 |
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set_location_assignment PIN_AE32 -to emif_0_mem_mem_dq[41]
|
| 147 |
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set_location_assignment PIN_AE30 -to emif_0_mem_mem_dq[42]
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| 148 |
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set_location_assignment PIN_AF30 -to emif_0_mem_mem_dq[43]
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| 149 |
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set_location_assignment PIN_AG33 -to emif_0_mem_mem_dq[44]
|
| 150 |
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set_location_assignment PIN_AG32 -to emif_0_mem_mem_dq[45]
|
| 151 |
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set_location_assignment PIN_AH33 -to emif_0_mem_mem_dq[46]
|
| 152 |
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set_location_assignment PIN_AH31 -to emif_0_mem_mem_dq[47]
|
| 153 |
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| 154 |
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set_location_assignment PIN_AJ32 -to emif_0_mem_mem_dqs[5]
|
| 155 |
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set_location_assignment PIN_AJ31 -to emif_0_mem_mem_dqs_n[5]
|
| 156 |
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| 157 |
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set_location_assignment PIN_AG31 -to emif_0_mem_mem_dbi_n[5]
|
| 158 |
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|
| 159 |
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#Group 6
|
| 160 |
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set_location_assignment PIN_U31 -to emif_0_mem_mem_dq[48]
|
| 161 |
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set_location_assignment PIN_W33 -to emif_0_mem_mem_dq[49]
|
| 162 |
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set_location_assignment PIN_W32 -to emif_0_mem_mem_dq[50]
|
| 163 |
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set_location_assignment PIN_V31 -to emif_0_mem_mem_dq[51]
|
| 164 |
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set_location_assignment PIN_Y34 -to emif_0_mem_mem_dq[52]
|
| 165 |
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set_location_assignment PIN_W35 -to emif_0_mem_mem_dq[53]
|
| 166 |
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set_location_assignment PIN_W34 -to emif_0_mem_mem_dq[54]
|
| 167 |
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set_location_assignment PIN_V34 -to emif_0_mem_mem_dq[55]
|
| 168 |
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| 169 |
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set_location_assignment PIN_AA34 -to emif_0_mem_mem_dqs[6]
|
| 170 |
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set_location_assignment PIN_AA33 -to emif_0_mem_mem_dqs_n[6]
|
| 171 |
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| 172 |
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set_location_assignment PIN_Y35 -to emif_0_mem_mem_dbi_n[6]
|
| 173 |
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|
| 174 |
|
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#Group 7
|
| 175 |
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set_location_assignment PIN_AH35 -to emif_0_mem_mem_dq[56]
|
| 176 |
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set_location_assignment PIN_AJ34 -to emif_0_mem_mem_dq[57]
|
| 177 |
|
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set_location_assignment PIN_AJ33 -to emif_0_mem_mem_dq[58]
|
| 178 |
|
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set_location_assignment PIN_AH34 -to emif_0_mem_mem_dq[59]
|
| 179 |
|
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set_location_assignment PIN_AD35 -to emif_0_mem_mem_dq[60]
|
| 180 |
|
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set_location_assignment PIN_AE34 -to emif_0_mem_mem_dq[61]
|
| 181 |
|
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set_location_assignment PIN_AC33 -to emif_0_mem_mem_dq[62]
|
| 182 |
|
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set_location_assignment PIN_AD34 -to emif_0_mem_mem_dq[63]
|
| 183 |
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|
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| 184 |
|
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set_location_assignment PIN_AF33 -to emif_0_mem_mem_dqs[7]
|
| 185 |
|
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set_location_assignment PIN_AF34 -to emif_0_mem_mem_dqs_n[7]
|
| 186 |
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|
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| 187 |
|
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set_location_assignment PIN_AC34 -to emif_0_mem_mem_dbi_n[7]
|
| 188 |
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|
|
| 189 |
|
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#Group 8
|
| 190 |
|
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set_location_assignment PIN_A33 -to emif_0_mem_mem_dq[64]
|
| 191 |
|
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set_location_assignment PIN_B32 -to emif_0_mem_mem_dq[65]
|
| 192 |
|
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set_location_assignment PIN_D32 -to emif_0_mem_mem_dq[66]
|
| 193 |
|
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set_location_assignment PIN_C33 -to emif_0_mem_mem_dq[67]
|
| 194 |
|
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set_location_assignment PIN_B33 -to emif_0_mem_mem_dq[68]
|
| 195 |
|
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set_location_assignment PIN_D34 -to emif_0_mem_mem_dq[69]
|
| 196 |
|
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set_location_assignment PIN_C35 -to emif_0_mem_mem_dq[70]
|
| 197 |
|
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set_location_assignment PIN_E34 -to emif_0_mem_mem_dq[71]
|
| 198 |
|
|
|
| 199 |
|
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set_location_assignment PIN_D33 -to emif_0_mem_mem_dqs[8]
|
| 200 |
|
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set_location_assignment PIN_C34 -to emif_0_mem_mem_dqs_n[8]
|
| 201 |
|
|
|
| 202 |
|
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set_location_assignment PIN_A32 -to emif_0_mem_mem_dbi_n[8]
|
| 203 |
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|
| 204 |
|
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# ###########ADDRESS, CLK, RZQ and REF Clock pins##################
|
| 205 |
|
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#middel tile RZQ
|
| 206 |
|
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set_location_assignment PIN_J34 -to emif_0_oct_oct_rzqin
|
| 207 |
|
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#bottom tile RZQ
|
| 208 |
|
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#set_location_assignment PIN_AF32 -to oct_oct_rzqin
|
| 209 |
|
|
|
| 210 |
|
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set_location_assignment PIN_M32 -to emif_0_mem_mem_a[0]
|
| 211 |
|
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set_location_assignment PIN_L32 -to emif_0_mem_mem_a[1]
|
| 212 |
|
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set_location_assignment PIN_N34 -to emif_0_mem_mem_a[2]
|
| 213 |
|
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set_location_assignment PIN_M35 -to emif_0_mem_mem_a[3]
|
| 214 |
|
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set_location_assignment PIN_L34 -to emif_0_mem_mem_a[4]
|
| 215 |
|
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set_location_assignment PIN_K34 -to emif_0_mem_mem_a[5]
|
| 216 |
|
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set_location_assignment PIN_M33 -to emif_0_mem_mem_a[6]
|
| 217 |
|
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set_location_assignment PIN_L33 -to emif_0_mem_mem_a[7]
|
| 218 |
|
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set_location_assignment PIN_J33 -to emif_0_mem_mem_a[8]
|
| 219 |
|
|
set_location_assignment PIN_J32 -to emif_0_mem_mem_a[9]
|
| 220 |
|
|
set_location_assignment PIN_H31 -to emif_0_mem_mem_a[10]
|
| 221 |
|
|
set_location_assignment PIN_J31 -to emif_0_mem_mem_a[11]
|
| 222 |
|
|
set_location_assignment PIN_H34 -to emif_0_mem_mem_a[12]
|
| 223 |
|
|
set_location_assignment PIN_H33 -to emif_0_mem_mem_a[13]
|
| 224 |
|
|
set_location_assignment PIN_G32 -to emif_0_mem_mem_a[14]
|
| 225 |
|
|
set_location_assignment PIN_E32 -to emif_0_mem_mem_a[15]
|
| 226 |
|
|
set_location_assignment PIN_F32 -to emif_0_mem_mem_a[16]
|
| 227 |
|
|
|
| 228 |
|
|
set_location_assignment PIN_F33 -to emif_0_mem_mem_ba[0]
|
| 229 |
|
|
set_location_assignment PIN_G35 -to emif_0_mem_mem_ba[1]
|
| 230 |
|
|
set_location_assignment PIN_H35 -to emif_0_mem_mem_bg[0]
|
| 231 |
|
|
#set_location_assignment PIN_T34 -to emif_0_mem_mem_bg[1]
|
| 232 |
|
|
|
| 233 |
|
|
set_location_assignment PIN_R30 -to emif_0_mem_mem_ck[0]
|
| 234 |
|
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set_location_assignment PIN_R31 -to emif_0_mem_mem_ck_n[0]
|
| 235 |
|
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set_location_assignment PIN_U33 -to emif_0_mem_mem_cke[0]
|
| 236 |
|
|
|
| 237 |
|
|
set_location_assignment PIN_R34 -to emif_0_mem_mem_cs_n[0]
|
| 238 |
|
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set_location_assignment PIN_P34 -to emif_0_mem_mem_act_n[0]
|
| 239 |
|
|
set_location_assignment PIN_N33 -to emif_0_mem_mem_odt[0]
|
| 240 |
|
|
set_location_assignment PIN_T35 -to emif_0_mem_mem_reset_n[0]
|
| 241 |
|
|
set_location_assignment PIN_T32 -to emif_0_mem_mem_par[0]
|
| 242 |
|
|
|
| 243 |
|
|
set_location_assignment PIN_E35 -to emif_0_mem_mem_alert_n[0]
|
| 244 |
|
|
|
| 245 |
|
|
set_location_assignment PIN_F35 -to "emif_0_pll_ref_clk_clk(n)"
|
| 246 |
|
|
set_location_assignment PIN_F34 -to emif_0_pll_ref_clk_clk
|
| 247 |
|
|
|
| 248 |
|
|
set_instance_assignment -name IO_STANDARD LVDS -to emif_0_pll_ref_clk_clk
|
| 249 |
|
|
set_instance_assignment -name IO_STANDARD LVDS -to "emif_0_pll_ref_clk_clk(n)"
|
| 250 |
|
|
|
| 251 |
|
|
|
| 252 |
|
|
# -------------------------------------------------------------------------- #
|
| 253 |
|
|
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition"
|
| 254 |
|
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
| 255 |
|
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
| 256 |
|
|
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
| 257 |
|
|
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
| 258 |
|
|
|
| 259 |
|
|
|
| 260 |
|
|
|
| 261 |
|
|
# ##############################################################################
|
| 262 |
|
|
# set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
|
| 263 |
|
|
|
| 264 |
|
|
|
| 265 |
|
|
|
| 266 |
|
|
# -------------------------------------------------------------------------- #
|
| 267 |
|
|
set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:make_pof.tcl"
|
| 268 |
|
|
|
| 269 |
|
|
|
| 270 |
|
|
# -------------------------------------------------------------------------- #
|
| 271 |
|
|
|
| 272 |
|
|
|
| 273 |
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
| 274 |
|
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
|
| 275 |
|
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
| 276 |
|
|
set_instance_assignment -name IO_STANDARD "1.8 V" -to clk_50
|
| 277 |
|
|
set_instance_assignment -name IO_STANDARD "1.8 V" -to cpu_resetn
|
| 278 |
|
|
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_g
|
| 279 |
|
|
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_r
|
| 280 |
|
|
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[0]
|
| 281 |
|
|
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[1]
|
| 282 |
|
|
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[2]
|
| 283 |
|
|
set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie_perstn
|
| 284 |
|
|
set_instance_assignment -name IO_STANDARD CML -to pcie_rx_p
|
| 285 |
|
|
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie_rx_p
|
| 286 |
|
|
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p
|
| 287 |
|
|
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie_tx_p
|
| 288 |
|
|
set_instance_assignment -name IO_STANDARD HCSL -to pcie_edge_refclk_p
|
| 289 |
|
|
set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to pcie_edge_refclk_p
|
| 290 |
|
|
set_global_assignment -name ENABLE_SIGNALTAP ON
|
| 291 |
|
|
|
| 292 |
|
|
# -------------------------------------------------------------------------- #
|
| 293 |
|
|
|
| 294 |
|
|
|
| 295 |
|
|
|
| 296 |
|
|
|
| 297 |
|
|
# -------------------------------------------------------------------------- #
|
| 298 |
|
|
|
| 299 |
|
|
|
| 300 |
|
|
|
| 301 |
|
|
|
| 302 |
|
|
|
| 303 |
|
|
set_global_assignment -name SEARCH_PATH ../../../../riffa_2.2.2/src
|
| 304 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_sys.sv
|
| 305 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa_top.sv
|
| 306 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa.sv
|
| 307 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_map_fifo.sv
|
| 308 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/misc/one_hot_encoder.sv
|
| 309 |
|
|
set_global_assignment -name VERILOG_FILE ../../../basal/src/PRBS/prbs_23_to_8.v
|
| 310 |
|
|
set_global_assignment -name VERILOG_FILE ../../../basal/src/synchronize/sync_reset.v
|
| 311 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/misc/recursive_mux.sv
|
| 312 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_upsizer.sv
|
| 313 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_downsizer.sv
|
| 314 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/FIFOs/tiny_sync_fifo.sv
|
| 315 |
|
|
set_global_assignment -name VERILOG_FILE ../../../basal/src/FIFOs/bc_sync_fifo.v
|
| 316 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/FIFOs/sync_fifo.sv
|
| 317 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_test_patern.sv
|
| 318 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_axis_test_pattern.sv
|
| 319 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_register_slice.sv
|
| 320 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_mux.sv
|
| 321 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_if.sv
|
| 322 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa_async_fifo.v
|
| 323 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_w.sv
|
| 324 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../../../riffa_2.2.2/src/riffa_pkg.sv
|
| 325 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_register_if.sv
|
| 326 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_register_file.sv
|
| 327 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_tx_fsm.sv
|
| 328 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_tx.sv
|
| 329 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_rx_fsm.sv
|
| 330 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_rx.sv
|
| 331 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_if.sv
|
| 332 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/txr_engine_classic.v
|
| 333 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/txc_engine_classic.v
|
| 334 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_writer.v
|
| 335 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_monitor_128.v
|
| 336 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_channel_gate_128.v
|
| 337 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_buffer_128.v
|
| 338 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_128.v
|
| 339 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_multiplexer_128.v
|
| 340 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_multiplexer.v
|
| 341 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_hdr_fifo.v
|
| 342 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine_selector.v
|
| 343 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine_classic.v
|
| 344 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine.v
|
| 345 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_shift.v
|
| 346 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_pipeline.v
|
| 347 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_fifo.v
|
| 348 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_alignment_pipeline.v
|
| 349 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/translation_altera.v
|
| 350 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/syncff.v
|
| 351 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa_sync_fifo.v
|
| 352 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/shiftreg.v
|
| 353 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/sg_list_requester.v
|
| 354 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/sg_list_reader_128.v
|
| 355 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/scsdpram.v
|
| 356 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rxr_engine_classic.v
|
| 357 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rxc_engine_classic.v
|
| 358 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_requester_mux.v
|
| 359 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_reader.v
|
| 360 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_channel_gate.v
|
| 361 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_128.v
|
| 362 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_engine_classic.v
|
| 363 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rotate.v
|
| 364 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa.v
|
| 365 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reset_extender.v
|
| 366 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reset_controller.v
|
| 367 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue_output.v
|
| 368 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue_input.v
|
| 369 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue.v
|
| 370 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/registers.v
|
| 371 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/register.v
|
| 372 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/recv_credit_flow_ctrl.v
|
| 373 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ram_2clk_1w_1r.v
|
| 374 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ram_1clk_1w_1r.v
|
| 375 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/pipeline.v
|
| 376 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/one_hot_mux.v
|
| 377 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/offset_to_mask.v
|
| 378 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/offset_flag_to_one_hot.v
|
| 379 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/mux.v
|
| 380 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/interrupt_controller.v
|
| 381 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/interrupt.v
|
| 382 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/fifo_packer_128.v
|
| 383 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/fifo.v
|
| 384 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ff.v
|
| 385 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/engine_layer.v
|
| 386 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/demux.v
|
| 387 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/cross_domain_signal.v
|
| 388 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/counter.v
|
| 389 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/chnl_tester.v
|
| 390 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/channel_128.v
|
| 391 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/channel.v
|
| 392 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/async_fifo_fwft.v
|
| 393 |
|
|
set_global_assignment -name QSYS_FILE ../../../../riffa_2.2.2/source/fpga/altera/a10ax/A10GXGen2x8If128_PCIe.qsys
|
| 394 |
|
|
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/source/fpga/altera/a10ax/riffa_wrapper_a10gx.v
|
| 395 |
|
|
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa_pcie.sv
|
| 396 |
|
|
set_global_assignment -name QSYS_FILE sys_pll.qsys
|
| 397 |
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
