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[/] [qaz_libs/] [trunk/] [PCIe/] [syn/] [a10gx_riffa/] [a10gx_riffa.qsf] - Blame information for rev 49

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Line No. Rev Author Line
1 49 qaztronic
# -------------------------------------------------------------------------- #
2
#
3
#
4
# -------------------------------------------------------------------------- #
5
 
6
set_global_assignment -name FAMILY "Arria 10"
7
set_global_assignment -name DEVICE 10AX115S2F45I1SG
8
set_global_assignment -name TOP_LEVEL_ENTITY a10gx_riffa_top
9
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
10
 
11
# -------------------------------------------------------------------------- #
12
set_location_assignment PIN_AU33 -to clk_50
13
 
14
set_location_assignment PIN_BD27 -to cpu_resetn
15
set_location_assignment PIN_L28 -to user_led_g[0]
16
set_location_assignment PIN_K26 -to user_led_g[1]
17
set_location_assignment PIN_K25 -to user_led_g[2]
18
set_location_assignment PIN_L25 -to user_led_g[3]
19
set_location_assignment PIN_J24 -to user_led_g[4]
20
set_location_assignment PIN_A19 -to user_led_g[5]
21
set_location_assignment PIN_C18 -to user_led_g[6]
22
set_location_assignment PIN_D18 -to user_led_g[7]
23
set_location_assignment PIN_L27 -to user_led_r[0]
24
set_location_assignment PIN_J26 -to user_led_r[1]
25
set_location_assignment PIN_K24 -to user_led_r[2]
26
set_location_assignment PIN_L23 -to user_led_r[3]
27
set_location_assignment PIN_B20 -to user_led_r[4]
28
set_location_assignment PIN_C19 -to user_led_r[5]
29
set_location_assignment PIN_D19 -to user_led_r[6]
30
set_location_assignment PIN_M23 -to user_led_r[7]
31
 
32
 
33
 
34
set_location_assignment PIN_T12 -to user_pb[0]
35
set_location_assignment PIN_U12 -to user_pb[1]
36
set_location_assignment PIN_U11 -to user_pb[2]
37
 
38
 
39
 
40
# -------------------------------------------------------------------------- #
41
# PCIe
42
set_location_assignment PIN_BC30 -to pcie_perstn
43
 
44
set_location_assignment PIN_AT40 -to pcie_rx_p[0]
45
set_location_assignment PIN_AP40 -to pcie_rx_p[1]
46
set_location_assignment PIN_AN42 -to pcie_rx_p[2]
47
set_location_assignment PIN_AM40 -to pcie_rx_p[3]
48
set_location_assignment PIN_AL42 -to pcie_rx_p[4]
49
set_location_assignment PIN_AK40 -to pcie_rx_p[5]
50
set_location_assignment PIN_AJ42 -to pcie_rx_p[6]
51
set_location_assignment PIN_AH40 -to pcie_rx_p[7]
52
 
53
set_location_assignment PIN_BB44 -to pcie_tx_p[0]
54
set_location_assignment PIN_BA42 -to pcie_tx_p[1]
55
set_location_assignment PIN_AY44 -to pcie_tx_p[2]
56
set_location_assignment PIN_AW42 -to pcie_tx_p[3]
57
set_location_assignment PIN_AV44 -to pcie_tx_p[4]
58
set_location_assignment PIN_AU42 -to pcie_tx_p[5]
59
set_location_assignment PIN_AT44 -to pcie_tx_p[6]
60
set_location_assignment PIN_AR42 -to pcie_tx_p[7]
61
 
62
 
63
set_location_assignment PIN_AL37 -to pcie_edge_refclk_p
64
 
65
 
66
# -------------------------------------------------------------------------- #
67
#Group0
68
set_location_assignment PIN_B28 -to emif_0_mem_mem_dq[0]
69
set_location_assignment PIN_A28 -to emif_0_mem_mem_dq[1]
70
set_location_assignment PIN_A27 -to emif_0_mem_mem_dq[2]
71
set_location_assignment PIN_B27 -to emif_0_mem_mem_dq[3]
72
set_location_assignment PIN_D27 -to emif_0_mem_mem_dq[4]
73
set_location_assignment PIN_E27 -to emif_0_mem_mem_dq[5]
74
set_location_assignment PIN_D26 -to emif_0_mem_mem_dq[6]
75
set_location_assignment PIN_D28 -to emif_0_mem_mem_dq[7]
76
 
77
set_location_assignment PIN_B26 -to emif_0_mem_mem_dqs[0]
78
set_location_assignment PIN_C26 -to emif_0_mem_mem_dqs_n[0]
79
 
80
set_location_assignment PIN_E26 -to emif_0_mem_mem_dbi_n[0]
81
 
82
 
83
#Group1
84
set_location_assignment PIN_G25 -to emif_0_mem_mem_dq[8]
85
set_location_assignment PIN_H25 -to emif_0_mem_mem_dq[9]
86
set_location_assignment PIN_G26 -to emif_0_mem_mem_dq[10]
87
set_location_assignment PIN_H26 -to emif_0_mem_mem_dq[11]
88
set_location_assignment PIN_G28 -to emif_0_mem_mem_dq[12]
89
set_location_assignment PIN_F27 -to emif_0_mem_mem_dq[13]
90
set_location_assignment PIN_K27 -to emif_0_mem_mem_dq[14]
91
set_location_assignment PIN_F28 -to emif_0_mem_mem_dq[15]
92
 
93
set_location_assignment PIN_H28 -to emif_0_mem_mem_dqs[1]
94
set_location_assignment PIN_J27 -to emif_0_mem_mem_dqs_n[1]
95
 
96
set_location_assignment PIN_G27 -to emif_0_mem_mem_dbi_n[1]
97
 
98
 
99
#Group 2
100
set_location_assignment PIN_D31 -to emif_0_mem_mem_dq[16]
101
set_location_assignment PIN_E31 -to emif_0_mem_mem_dq[17]
102
set_location_assignment PIN_B31 -to emif_0_mem_mem_dq[18]
103
set_location_assignment PIN_C31 -to emif_0_mem_mem_dq[19]
104
set_location_assignment PIN_A30 -to emif_0_mem_mem_dq[20]
105
set_location_assignment PIN_E30 -to emif_0_mem_mem_dq[21]
106
set_location_assignment PIN_B30 -to emif_0_mem_mem_dq[22]
107
set_location_assignment PIN_D29 -to emif_0_mem_mem_dq[23]
108
 
109
set_location_assignment PIN_C30 -to emif_0_mem_mem_dqs[2]
110
set_location_assignment PIN_C29 -to emif_0_mem_mem_dqs_n[2]
111
 
112
set_location_assignment PIN_A29 -to emif_0_mem_mem_dbi_n[2]
113
 
114
#Group 3
115
set_location_assignment PIN_K30 -to emif_0_mem_mem_dq[24]
116
set_location_assignment PIN_H30 -to emif_0_mem_mem_dq[25]
117
set_location_assignment PIN_G30 -to emif_0_mem_mem_dq[26]
118
set_location_assignment PIN_K31 -to emif_0_mem_mem_dq[27]
119
set_location_assignment PIN_H29 -to emif_0_mem_mem_dq[28]
120
set_location_assignment PIN_K29 -to emif_0_mem_mem_dq[29]
121
set_location_assignment PIN_J29 -to emif_0_mem_mem_dq[30]
122
set_location_assignment PIN_F29 -to emif_0_mem_mem_dq[31]
123
 
124
set_location_assignment PIN_L30 -to emif_0_mem_mem_dqs[3]
125
set_location_assignment PIN_L29 -to emif_0_mem_mem_dqs_n[3]
126
 
127
set_location_assignment PIN_F30 -to emif_0_mem_mem_dbi_n[3]
128
 
129
#Group 4
130
set_location_assignment PIN_AC31 -to emif_0_mem_mem_dq[32]
131
set_location_assignment PIN_AB31 -to emif_0_mem_mem_dq[33]
132
set_location_assignment PIN_W31 -to emif_0_mem_mem_dq[34]
133
set_location_assignment PIN_Y31 -to emif_0_mem_mem_dq[35]
134
set_location_assignment PIN_AD31 -to emif_0_mem_mem_dq[36]
135
set_location_assignment PIN_AD32 -to emif_0_mem_mem_dq[37]
136
set_location_assignment PIN_AD33 -to emif_0_mem_mem_dq[38]
137
set_location_assignment PIN_AA30 -to emif_0_mem_mem_dq[39]
138
 
139
set_location_assignment PIN_Y32 -to emif_0_mem_mem_dqs[4]
140
set_location_assignment PIN_AA32 -to emif_0_mem_mem_dqs_n[4]
141
 
142
set_location_assignment PIN_AB32 -to emif_0_mem_mem_dbi_n[4]
143
 
144
#Group 5
145
set_location_assignment PIN_AE31 -to emif_0_mem_mem_dq[40]
146
set_location_assignment PIN_AE32 -to emif_0_mem_mem_dq[41]
147
set_location_assignment PIN_AE30 -to emif_0_mem_mem_dq[42]
148
set_location_assignment PIN_AF30 -to emif_0_mem_mem_dq[43]
149
set_location_assignment PIN_AG33 -to emif_0_mem_mem_dq[44]
150
set_location_assignment PIN_AG32 -to emif_0_mem_mem_dq[45]
151
set_location_assignment PIN_AH33 -to emif_0_mem_mem_dq[46]
152
set_location_assignment PIN_AH31 -to emif_0_mem_mem_dq[47]
153
 
154
set_location_assignment PIN_AJ32 -to emif_0_mem_mem_dqs[5]
155
set_location_assignment PIN_AJ31 -to emif_0_mem_mem_dqs_n[5]
156
 
157
set_location_assignment PIN_AG31 -to emif_0_mem_mem_dbi_n[5]
158
 
159
#Group 6
160
set_location_assignment PIN_U31 -to emif_0_mem_mem_dq[48]
161
set_location_assignment PIN_W33 -to emif_0_mem_mem_dq[49]
162
set_location_assignment PIN_W32 -to emif_0_mem_mem_dq[50]
163
set_location_assignment PIN_V31 -to emif_0_mem_mem_dq[51]
164
set_location_assignment PIN_Y34 -to emif_0_mem_mem_dq[52]
165
set_location_assignment PIN_W35 -to emif_0_mem_mem_dq[53]
166
set_location_assignment PIN_W34 -to emif_0_mem_mem_dq[54]
167
set_location_assignment PIN_V34 -to emif_0_mem_mem_dq[55]
168
 
169
set_location_assignment PIN_AA34 -to emif_0_mem_mem_dqs[6]
170
set_location_assignment PIN_AA33 -to emif_0_mem_mem_dqs_n[6]
171
 
172
set_location_assignment PIN_Y35 -to emif_0_mem_mem_dbi_n[6]
173
 
174
#Group 7
175
set_location_assignment PIN_AH35 -to emif_0_mem_mem_dq[56]
176
set_location_assignment PIN_AJ34 -to emif_0_mem_mem_dq[57]
177
set_location_assignment PIN_AJ33 -to emif_0_mem_mem_dq[58]
178
set_location_assignment PIN_AH34 -to emif_0_mem_mem_dq[59]
179
set_location_assignment PIN_AD35 -to emif_0_mem_mem_dq[60]
180
set_location_assignment PIN_AE34 -to emif_0_mem_mem_dq[61]
181
set_location_assignment PIN_AC33 -to emif_0_mem_mem_dq[62]
182
set_location_assignment PIN_AD34 -to emif_0_mem_mem_dq[63]
183
 
184
set_location_assignment PIN_AF33 -to emif_0_mem_mem_dqs[7]
185
set_location_assignment PIN_AF34 -to emif_0_mem_mem_dqs_n[7]
186
 
187
set_location_assignment PIN_AC34 -to emif_0_mem_mem_dbi_n[7]
188
 
189
#Group 8
190
set_location_assignment PIN_A33 -to emif_0_mem_mem_dq[64]
191
set_location_assignment PIN_B32 -to emif_0_mem_mem_dq[65]
192
set_location_assignment PIN_D32 -to emif_0_mem_mem_dq[66]
193
set_location_assignment PIN_C33 -to emif_0_mem_mem_dq[67]
194
set_location_assignment PIN_B33 -to emif_0_mem_mem_dq[68]
195
set_location_assignment PIN_D34 -to emif_0_mem_mem_dq[69]
196
set_location_assignment PIN_C35 -to emif_0_mem_mem_dq[70]
197
set_location_assignment PIN_E34 -to emif_0_mem_mem_dq[71]
198
 
199
set_location_assignment PIN_D33 -to emif_0_mem_mem_dqs[8]
200
set_location_assignment PIN_C34 -to emif_0_mem_mem_dqs_n[8]
201
 
202
set_location_assignment PIN_A32 -to emif_0_mem_mem_dbi_n[8]
203
 
204
# ###########ADDRESS, CLK, RZQ and REF Clock pins##################
205
#middel tile RZQ
206
set_location_assignment PIN_J34 -to emif_0_oct_oct_rzqin
207
#bottom tile RZQ
208
#set_location_assignment PIN_AF32 -to oct_oct_rzqin
209
 
210
set_location_assignment PIN_M32 -to emif_0_mem_mem_a[0]
211
set_location_assignment PIN_L32 -to emif_0_mem_mem_a[1]
212
set_location_assignment PIN_N34 -to emif_0_mem_mem_a[2]
213
set_location_assignment PIN_M35 -to emif_0_mem_mem_a[3]
214
set_location_assignment PIN_L34 -to emif_0_mem_mem_a[4]
215
set_location_assignment PIN_K34 -to emif_0_mem_mem_a[5]
216
set_location_assignment PIN_M33 -to emif_0_mem_mem_a[6]
217
set_location_assignment PIN_L33 -to emif_0_mem_mem_a[7]
218
set_location_assignment PIN_J33 -to emif_0_mem_mem_a[8]
219
set_location_assignment PIN_J32 -to emif_0_mem_mem_a[9]
220
set_location_assignment PIN_H31 -to emif_0_mem_mem_a[10]
221
set_location_assignment PIN_J31 -to emif_0_mem_mem_a[11]
222
set_location_assignment PIN_H34 -to emif_0_mem_mem_a[12]
223
set_location_assignment PIN_H33 -to emif_0_mem_mem_a[13]
224
set_location_assignment PIN_G32 -to emif_0_mem_mem_a[14]
225
set_location_assignment PIN_E32 -to emif_0_mem_mem_a[15]
226
set_location_assignment PIN_F32 -to emif_0_mem_mem_a[16]
227
 
228
set_location_assignment PIN_F33 -to emif_0_mem_mem_ba[0]
229
set_location_assignment PIN_G35 -to emif_0_mem_mem_ba[1]
230
set_location_assignment PIN_H35 -to emif_0_mem_mem_bg[0]
231
#set_location_assignment PIN_T34 -to emif_0_mem_mem_bg[1]
232
 
233
set_location_assignment PIN_R30 -to emif_0_mem_mem_ck[0]
234
set_location_assignment PIN_R31 -to emif_0_mem_mem_ck_n[0]
235
set_location_assignment PIN_U33 -to emif_0_mem_mem_cke[0]
236
 
237
set_location_assignment PIN_R34 -to emif_0_mem_mem_cs_n[0]
238
set_location_assignment PIN_P34 -to emif_0_mem_mem_act_n[0]
239
set_location_assignment PIN_N33 -to emif_0_mem_mem_odt[0]
240
set_location_assignment PIN_T35 -to emif_0_mem_mem_reset_n[0]
241
set_location_assignment PIN_T32 -to emif_0_mem_mem_par[0]
242
 
243
set_location_assignment PIN_E35 -to emif_0_mem_mem_alert_n[0]
244
 
245
set_location_assignment PIN_F35 -to "emif_0_pll_ref_clk_clk(n)"
246
set_location_assignment PIN_F34 -to emif_0_pll_ref_clk_clk
247
 
248
set_instance_assignment -name IO_STANDARD LVDS -to emif_0_pll_ref_clk_clk
249
set_instance_assignment -name IO_STANDARD LVDS -to "emif_0_pll_ref_clk_clk(n)"
250
 
251
 
252
# -------------------------------------------------------------------------- #
253
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Standard Edition"
254
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
255
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
257
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
258
 
259
 
260
 
261
# ##############################################################################
262
# set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
263
 
264
 
265
 
266
# -------------------------------------------------------------------------- #
267
set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:make_pof.tcl"
268
 
269
 
270
# -------------------------------------------------------------------------- #
271
 
272
 
273
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
274
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
275
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
276
set_instance_assignment -name IO_STANDARD "1.8 V" -to clk_50
277
set_instance_assignment -name IO_STANDARD "1.8 V" -to cpu_resetn
278
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_g
279
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_led_r
280
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[0]
281
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[1]
282
set_instance_assignment -name IO_STANDARD "1.8 V" -to user_pb[2]
283
set_instance_assignment -name IO_STANDARD "1.8 V" -to pcie_perstn
284
set_instance_assignment -name IO_STANDARD CML -to pcie_rx_p
285
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie_rx_p
286
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to pcie_tx_p
287
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to pcie_tx_p
288
set_instance_assignment -name IO_STANDARD HCSL -to pcie_edge_refclk_p
289
set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to pcie_edge_refclk_p
290
set_global_assignment -name ENABLE_SIGNALTAP ON
291
 
292
# -------------------------------------------------------------------------- #
293
 
294
 
295
 
296
 
297
# -------------------------------------------------------------------------- #
298
 
299
 
300
 
301
 
302
 
303
set_global_assignment -name SEARCH_PATH ../../../../riffa_2.2.2/src
304
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_sys.sv
305
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa_top.sv
306
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa.sv
307
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_map_fifo.sv
308
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/misc/one_hot_encoder.sv
309
set_global_assignment -name VERILOG_FILE ../../../basal/src/PRBS/prbs_23_to_8.v
310
set_global_assignment -name VERILOG_FILE ../../../basal/src/synchronize/sync_reset.v
311
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/misc/recursive_mux.sv
312
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_upsizer.sv
313
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_downsizer.sv
314
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/FIFOs/tiny_sync_fifo.sv
315
set_global_assignment -name VERILOG_FILE ../../../basal/src/FIFOs/bc_sync_fifo.v
316
set_global_assignment -name SYSTEMVERILOG_FILE ../../../basal/src/FIFOs/sync_fifo.sv
317
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_test_patern.sv
318
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_axis_test_pattern.sv
319
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_register_slice.sv
320
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_mux.sv
321
set_global_assignment -name SYSTEMVERILOG_FILE ../../../axi4_stream_lib/src/axis_if.sv
322
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa_async_fifo.v
323
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_w.sv
324
set_global_assignment -name SYSTEMVERILOG_FILE ../../../../riffa_2.2.2/src/riffa_pkg.sv
325
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_register_if.sv
326
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_register_file.sv
327
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_tx_fsm.sv
328
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_tx.sv
329
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_rx_fsm.sv
330
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_rx.sv
331
set_global_assignment -name SYSTEMVERILOG_FILE ../../src/RIFFA/riffa_chnl_if.sv
332
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/txr_engine_classic.v
333
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/txc_engine_classic.v
334
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_writer.v
335
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_monitor_128.v
336
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_channel_gate_128.v
337
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_buffer_128.v
338
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_port_128.v
339
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_multiplexer_128.v
340
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_multiplexer.v
341
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_hdr_fifo.v
342
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine_selector.v
343
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine_classic.v
344
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_engine.v
345
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_shift.v
346
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_pipeline.v
347
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_data_fifo.v
348
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/tx_alignment_pipeline.v
349
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/translation_altera.v
350
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/syncff.v
351
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa_sync_fifo.v
352
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/shiftreg.v
353
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/sg_list_requester.v
354
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/sg_list_reader_128.v
355
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/scsdpram.v
356
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rxr_engine_classic.v
357
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rxc_engine_classic.v
358
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_requester_mux.v
359
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_reader.v
360
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_channel_gate.v
361
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_port_128.v
362
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rx_engine_classic.v
363
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/rotate.v
364
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/riffa.v
365
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reset_extender.v
366
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reset_controller.v
367
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue_output.v
368
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue_input.v
369
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/reorder_queue.v
370
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/registers.v
371
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/register.v
372
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/recv_credit_flow_ctrl.v
373
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ram_2clk_1w_1r.v
374
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ram_1clk_1w_1r.v
375
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/pipeline.v
376
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/one_hot_mux.v
377
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/offset_to_mask.v
378
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/offset_flag_to_one_hot.v
379
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/mux.v
380
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/interrupt_controller.v
381
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/interrupt.v
382
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/fifo_packer_128.v
383
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/fifo.v
384
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/ff.v
385
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/engine_layer.v
386
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/demux.v
387
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/cross_domain_signal.v
388
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/counter.v
389
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/chnl_tester.v
390
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/channel_128.v
391
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/channel.v
392
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/src/async_fifo_fwft.v
393
set_global_assignment -name QSYS_FILE ../../../../riffa_2.2.2/source/fpga/altera/a10ax/A10GXGen2x8If128_PCIe.qsys
394
set_global_assignment -name VERILOG_FILE ../../../../riffa_2.2.2/source/fpga/altera/a10ax/riffa_wrapper_a10gx.v
395
set_global_assignment -name SYSTEMVERILOG_FILE a10gx_riffa_pcie.sv
396
set_global_assignment -name QSYS_FILE sys_pll.qsys
397
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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