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qaztronic |
# ----------------------------------------------------------------------
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# Copyright (c) 2016, The Regents of the University of California All
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# rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met:
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#
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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#
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# * Redistributions in binary form must reproduce the above
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# copyright notice, this list of conditions and the following
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# disclaimer in the documentation and/or other materials provided
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# with the distribution.
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#
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# * Neither the name of The Regents of the University of California
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# nor the names of its contributors may be used to endorse or
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# promote products derived from this software without specific
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# prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
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# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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# DAMAGE.
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# ----------------------------------------------------------------------
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# ---------------------------------------------------------------------------
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# Filename: DE5QGen3x4If128.sdc (Qsys)
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# Version: 1.00.a
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# Verilog Standard: Verilog-2001
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# Description: Synopsys Design Constraints for the DE5 board.
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# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
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# Author: Dustin Richmond (@darichmond)
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# ----------------------------------------------------------------------------
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# create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
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# create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
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create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
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create_clock -name {clk_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk_50}]
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# create_clock -name {pcie_ob_refclk_p} -period 10.000 [get_ports {pcie_ob_refclk_p}]
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# create_clock -name {emif_0_pll_ref_clk_clk} -period 6.666 [ get_ports emif_0_pll_ref_clk_clk]
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# derive_pll_clocks -create_base_clocks
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# derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tdi]
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set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tms]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -clock altera_reserved_tck -clock_fall -max 6 [get_ports altera_reserved_tdo]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
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set_clock_groups -asynchronous -group [get_clocks { clk_50 }]
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# set_clock_groups -asynchronous -group [get_clocks { pcie_ob_refclk_p }]
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# set_clock_groups -asynchronous -group [get_clocks { emif_0_pll_ref_clk_clk }]
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#**************************************************************
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# Set False Path
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#**************************************************************
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set_false_path -from * -to [get_ports {user_led_g[*]}]
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set_false_path -from * -to [get_ports {user_led_r[*]}]
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set_false_path -from [get_ports {altera_reserved_ntrst}]
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set_false_path -from [get_ports {cpu_resetn}]
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# set_false_path -from [get_ports {emif_0_oct_oct_rzqin}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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