OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [PCIe/] [syn/] [a10gx_riffa/] [a10gx_riffa.sdc] - Blame information for rev 49

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 49 qaztronic
# ----------------------------------------------------------------------
2
# Copyright (c) 2016, The Regents of the University of California All
3
# rights reserved.
4
#
5
# Redistribution and use in source and binary forms, with or without
6
# modification, are permitted provided that the following conditions are
7
# met:
8
#
9
#     * Redistributions of source code must retain the above copyright
10
#       notice, this list of conditions and the following disclaimer.
11
#
12
#     * Redistributions in binary form must reproduce the above
13
#       copyright notice, this list of conditions and the following
14
#       disclaimer in the documentation and/or other materials provided
15
#       with the distribution.
16
#
17
#     * Neither the name of The Regents of the University of California
18
#       nor the names of its contributors may be used to endorse or
19
#       promote products derived from this software without specific
20
#       prior written permission.
21
#
22
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
26
# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
27
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
31
# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
32
# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33
# DAMAGE.
34
# ----------------------------------------------------------------------
35
# ---------------------------------------------------------------------------
36
# Filename:            DE5QGen3x4If128.sdc (Qsys)
37
# Version:             1.00.a
38
# Verilog Standard:    Verilog-2001
39
# Description:         Synopsys Design Constraints for the DE5 board.
40
# These design constrains constrain the PCIE_REFCLK, and 50 MHz Clock Input
41
# Author:              Dustin Richmond (@darichmond)
42
# ----------------------------------------------------------------------------
43
# create_clock -name PCIE_REFCLK -period 10.000 [get_ports {PCIE_REFCLK}]
44
# create_clock -name osc_50MHz -period 20.000 [get_ports {OSC_BANK3D_50MHZ}]
45
 
46
create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
47
create_clock -name {clk_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk_50}]
48
# create_clock -name {pcie_ob_refclk_p} -period 10.000 [get_ports {pcie_ob_refclk_p}]
49
# create_clock -name {emif_0_pll_ref_clk_clk} -period 6.666 [ get_ports emif_0_pll_ref_clk_clk]
50
 
51
# derive_pll_clocks -create_base_clocks
52
# derive_clock_uncertainty
53
 
54
#**************************************************************
55
# Set Input Delay
56
#**************************************************************
57
set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tdi]
58
set_input_delay -clock altera_reserved_tck 6 [get_ports altera_reserved_tms]
59
 
60
 
61
 
62
#**************************************************************
63
# Set Output Delay
64
#**************************************************************
65
set_output_delay -clock altera_reserved_tck -clock_fall -max 6 [get_ports altera_reserved_tdo]
66
 
67
 
68
 
69
#**************************************************************
70
# Set Clock Groups
71
#**************************************************************
72
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
73
set_clock_groups -asynchronous -group [get_clocks { clk_50 }]
74
# set_clock_groups -asynchronous -group [get_clocks { pcie_ob_refclk_p }]
75
# set_clock_groups -asynchronous -group [get_clocks { emif_0_pll_ref_clk_clk }]
76
 
77
 
78
#**************************************************************
79
# Set False Path
80
#**************************************************************
81
set_false_path -from * -to [get_ports {user_led_g[*]}]
82
set_false_path -from * -to [get_ports {user_led_r[*]}]
83
set_false_path -from [get_ports {altera_reserved_ntrst}]
84
set_false_path -from [get_ports {cpu_resetn}]
85
# set_false_path -from [get_ports {emif_0_oct_oct_rzqin}]
86
 
87
 
88
#**************************************************************
89
# Set Multicycle Path
90
#**************************************************************
91
 
92
 
93
 
94
#**************************************************************
95
# Set Maximum Delay
96
#**************************************************************
97
 
98
 
99
 
100
#**************************************************************
101
# Set Minimum Delay
102
#**************************************************************
103
 
104
 
105
 
106
#**************************************************************
107
# Set Input Transition
108
#**************************************************************
109
 
110
 
111
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.