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[/] [qaz_libs/] [trunk/] [PCIe/] [syn/] [a10gx_riffa/] [a10gx_riffa.sv] - Blame information for rev 49

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1 49 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  a10gx_riffa
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  #(// Number of RIFFA Channels
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    C_NUM_CHNL,
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    // Number of PCIe Lanes
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    C_NUM_LANES,
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    // Settings from Quartus IP Library
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    C_PCI_DATA_WIDTH,
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    C_MAX_PAYLOAD_BYTES,
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    C_LOG_NUM_TAGS,
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    C_FPGA_ID
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  )
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  (
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    input  [ 7:0]  pcie_rx_p,          //PCML14  //PCIe Receive Data-req's OCT
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    output [ 7:0]  pcie_tx_p,          //PCML14  //PCIe Transmit Data
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    input          pcie_edge_refclk_p, //HCSL    //PCIe Clock- Terminate on MB
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    input          pcie_perstn,        //1.8V    //PCIe Reset
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    input          npor,
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    riffa_chnl_if chnl_bus[C_NUM_CHNL],
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    output chnl_reset,
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    output chnl_clk
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  );
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  // --------------------------------------------------------------------
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  import riffa_pkg::*;
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  // --------------------------------------------------------------------
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  wire [3:0]                  tl_cfg_add;
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  wire [31:0]                 tl_cfg_ctl;
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  wire [52:0]                 tl_cfg_sts;
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  wire [0:0]                  rx_st_sop;
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  wire [0:0]                  rx_st_eop;
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  wire [0:0]                  rx_st_err;
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  wire [0:0]                  rx_st_valid;
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  wire [0:0]                  rx_st_empty;
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  wire                        rx_st_ready;
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  wire [C_PCI_DATA_WIDTH-1:0] rx_st_data;
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  wire [0:0]                  tx_st_sop;
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  wire [0:0]                  tx_st_eop;
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  wire [0:0]                  tx_st_err;
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  wire [0:0]                  tx_st_valid;
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  wire                        tx_st_ready;
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  wire [C_PCI_DATA_WIDTH-1:0] tx_st_data;
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  wire [0:0]                  tx_st_empty;
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  wire                        pld_clk;
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  wire                        reset_status;
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  wire                        app_msi_req;
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  wire                        app_msi_ack;
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  wire [7:0]                  ko_cpl_spc_header;
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  wire [11:0]                 ko_cpl_spc_data;
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  a10gx_riffa_pcie #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
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    a10gx_riffa_pcie_i(.*);
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  // --------------------------------------------------------------------
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  wire [C_NUM_CHNL-1:0]                     CHNL_RX_CLK;
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  wire [C_NUM_CHNL-1:0]                     CHNL_RX;
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  wire [C_NUM_CHNL-1:0]                     CHNL_RX_ACK;
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  wire [C_NUM_CHNL-1:0]                     CHNL_RX_LAST;
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  wire [(C_NUM_CHNL*32)-1:0]                CHNL_RX_LEN;
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  wire [(C_NUM_CHNL*31)-1:0]                CHNL_RX_OFF;
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  wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]  CHNL_RX_DATA;
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  wire [C_NUM_CHNL-1:0]                     CHNL_RX_DATA_VALID;
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  wire [C_NUM_CHNL-1:0]                     CHNL_RX_DATA_REN;
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  wire [C_NUM_CHNL-1:0]                     CHNL_TX_CLK;
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  wire [C_NUM_CHNL-1:0]                     CHNL_TX;
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  wire [C_NUM_CHNL-1:0]                     CHNL_TX_ACK;
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  wire [C_NUM_CHNL-1:0]                     CHNL_TX_LAST;
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  wire [(C_NUM_CHNL*32)-1:0]                CHNL_TX_LEN;
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  wire [(C_NUM_CHNL*31)-1:0]                CHNL_TX_OFF;
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  wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]  CHNL_TX_DATA;
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  wire [C_NUM_CHNL-1:0]                     CHNL_TX_DATA_VALID;
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  wire [C_NUM_CHNL-1:0]                     CHNL_TX_DATA_REN;
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  riffa_chnl_w
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    #(
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      .C_NUM_CHNL(C_NUM_CHNL),
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      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
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      .SIG_CHNL_LENGTH_W(SIG_CHNL_LENGTH_W),
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      .SIG_CHNL_OFFSET_W(SIG_CHNL_OFFSET_W)
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    )
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    riffa_chnl_w_i(.*);
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  // --------------------------------------------------------------------
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  wire rst_out;
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  wire riffa_reset;
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  wire riffa_clk;
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  assign riffa_reset = reset_status;
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  assign riffa_clk = pld_clk;
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  assign chnl_clk = pld_clk;
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  assign chnl_reset = rst_out;
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  riffa_wrapper_a10gx
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    #(
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      .C_LOG_NUM_TAGS               (C_LOG_NUM_TAGS),
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      .C_NUM_CHNL                   (C_NUM_CHNL),
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      .C_PCI_DATA_WIDTH             (C_PCI_DATA_WIDTH),
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      .C_MAX_PAYLOAD_BYTES          (C_MAX_PAYLOAD_BYTES),
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      .C_FPGA_ID                    (C_FPGA_ID)
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    )
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    riffa
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    (
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      .RX_ST_READY                   (rx_st_ready),
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      .TX_ST_DATA                    (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
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      .TX_ST_VALID                   (tx_st_valid[0:0]),
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      .TX_ST_EOP                     (tx_st_eop[0:0]),
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      .TX_ST_SOP                     (tx_st_sop[0:0]),
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      .TX_ST_EMPTY                   (tx_st_empty[0:0]),
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      .APP_MSI_REQ                   (app_msi_req),
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      .RST_OUT                       (rst_out),
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      // Inputs
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      .RX_ST_DATA                    (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
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      .RX_ST_EOP                     (rx_st_eop[0:0]),
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      .RX_ST_SOP                     (rx_st_sop[0:0]),
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      .RX_ST_VALID                   (rx_st_valid[0:0]),
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      .RX_ST_EMPTY                   (rx_st_empty[0:0]),
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      .TX_ST_READY                   (tx_st_ready),
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      .TL_CFG_CTL                    (tl_cfg_ctl[SIG_CFG_CTL_W-1:0]),
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      .TL_CFG_ADD                    (tl_cfg_add[SIG_CFG_ADD_W-1:0]),
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      .TL_CFG_STS                    (tl_cfg_sts[SIG_CFG_STS_W-1:0]),
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      .KO_CPL_SPC_HEADER             (ko_cpl_spc_header[SIG_KO_CPLH_W-1:0]),
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      .KO_CPL_SPC_DATA               (ko_cpl_spc_data[SIG_KO_CPLD_W-1:0]),
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      .APP_MSI_ACK                   (app_msi_ack),
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      .PLD_CLK                       (pld_clk),
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      .RESET_STATUS                  (reset_status),
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      .*
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    );
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// --------------------------------------------------------------------
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endmodule

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