Subversion Repositories qaz_libs

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

module

  a10gx_riffa_top

  #(// Number of RIFFA Channels

    C_NUM_CHNL = 1,

    // Number of PCIe Lanes

    C_NUM_LANES =  8,

    // Settings from Quartus IP Library

    C_PCI_DATA_WIDTH = 128,

    C_MAX_PAYLOAD_BYTES = 256,

    C_LOG_NUM_TAGS = 5,

    C_FPGA_ID = 8'hab

    )

  (

    input          clk_50,             //1.8V - 50MHz

    input          cpu_resetn,         //1.8V    //CPU Reset Pushbutton (TR=0)

    output [ 7:0]  user_led_g,         //1.8V    //User LEDs

    output [ 7:0]  user_led_r,         //1.8V    //User LEDs

    input  [ 2:0]  user_pb,            //1.8V    //User Pushbuttons (TR=0)

    input  [ 7:0]  pcie_rx_p,          //PCML14  //PCIe Receive Data-req's OCT

    output [ 7:0]  pcie_tx_p,          //PCML14  //PCIe Transmit Data

    input          pcie_edge_refclk_p, //HCSL    //PCIe Clock- Terminate on MB

    input          pcie_perstn         //1.8V    //PCIe Reset

  );

  // --------------------------------------------------------------------

  localparam R_N = (C_PCI_DATA_WIDTH / 8); // width of the RIFFA bus in bytes

  localparam RR_B = 4; // number of available registers

  localparam I = 0; // TID width

  localparam D = 0; // TDEST width

  localparam U = 3; // TUSER width

  // --------------------------------------------------------------------

  wire sys_aresetn;

  wire chnl_clk;

  wire chnl_reset;

  wire chnl_reset_s;

  wire clk = chnl_clk;

  wire reset = chnl_reset_s;

  wire aclk = chnl_clk;

  wire aresetn = ~chnl_reset_s;

  sync_reset

    sync_reset_i

    (

      .clk_in(chnl_clk),

      .async_reset_in(chnl_reset),

      .sync_reset_out(chnl_reset_s)

    );

  // --------------------------------------------------------------------

  riffa_chnl_if #(.N(R_N)) chnl_bus[C_NUM_CHNL]();

  riffa_register_if #(.N(R_N), .B(RR_B)) r_if(.*);

  // --------------------------------------------------------------------

  wire npor;

  a10gx_riffa

    #(// Number of RIFFA Channels

      .C_NUM_CHNL(C_NUM_CHNL),

      // Number of PCIe Lanes

      .C_NUM_LANES(C_NUM_LANES),

      // Settings from Quartus IP Library

      .C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),

      .C_MAX_PAYLOAD_BYTES(C_MAX_PAYLOAD_BYTES),

      .C_LOG_NUM_TAGS(C_LOG_NUM_TAGS),

      .C_FPGA_ID(C_FPGA_ID)

    )

    a10gx_riffa_i(.*);

  // --------------------------------------------------------------------

  a10gx_sys #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .B(RR_B))

    a10gx_sys_i(.chnl_bus(chnl_bus[0]), .*);

// --------------------------------------------------------------------

endmodule