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[/] [qaz_libs/] [trunk/] [PCIe/] [syn/] [a10gx_riffa/] [a10gx_sys.sv] - Blame information for rev 49

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1 49 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  a10gx_sys
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  #(
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    C_PCI_DATA_WIDTH,
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    B,
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    N = (C_PCI_DATA_WIDTH / 8), // width of the bus in bytes
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    RW = (N/4), // width of the bus in 32 bit words
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    RC = RW * B // number of available registers
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  )
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  (
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    input          clk_50,             //1.8V - 50MHz
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    input          cpu_resetn,         //1.8V    //CPU Reset Pushbutton (TR=0)
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    output [ 7:0]  user_led_g,         //1.8V    //User LEDs
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    output [ 7:0]  user_led_r,         //1.8V    //User LEDs
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    input  [ 2:0]  user_pb,            //1.8V    //User Pushbuttons (TR=0)
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    output         npor,
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    input          pcie_perstn,         //1.8V    //PCIe Reset
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    output         sys_aresetn,
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    riffa_chnl_if chnl_bus,
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    riffa_register_if r_if,
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    input clk,
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    input reset
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  );
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  // --------------------------------------------------------------------
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  //
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  wire clk_50mhz;
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  sys_pll
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    sys_pll_i
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    (
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      .rst(~user_pb[0]),
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      .refclk(clk_50),
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      .outclk_0(clk_50mhz),
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      .locked(sys_aresetn)
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    );
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  // --------------------------------------------------------------------
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  //
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  riffa_register_file  #(.N(N), .B(B))
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    riffa_register_file_i(.*);
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  // --------------------------------------------------------------------
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  //
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  reg [31:0] fled_counter;
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  always_ff @(posedge clk_50mhz)
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    fled_counter <= fled_counter + 1;
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  // --------------------------------------------------------------------
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  //
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  genvar j;
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  generate
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    for(j = 0; j < RC; j++)
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    begin : registers
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      assign r_if.register_in[j] = r_if.register_out[j];
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  //
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  assign user_led_g[0] = fled_counter[23];
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  assign user_led_g[7:1] = r_if.register_out[0][7:1];
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  assign user_led_r = r_if.register_out[0][15:8];
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  assign npor = pcie_perstn & sys_aresetn;
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// --------------------------------------------------------------------
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//
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endmodule

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