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[/] [qaz_libs/] [trunk/] [avalon_lib/] [sim/] [src/] [amm_bfm/] [amm_master_bfm_if.sv] - Blame information for rev 31

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1 31 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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interface
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  amm_master_bfm_if
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  #(
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    A = 32, // address bus width
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    N = 8   // data bus width in bytes
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  )
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  (
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    amm_if amm_s,
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    input reset,
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    input clk
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  );
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        logic [(A-1):0]   address;
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        logic             read;
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        logic   [(8*N)-1:0] readdata;
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        logic             write;
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        logic   [(8*N)-1:0] writedata;
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        logic   [N-1:0]     byteenable;
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        logic             waitrequest;
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        logic             arbiterlock;
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        logic             readdatavalid;
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        logic   [6:0]       burstcount;
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        logic               resetrequest;
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  // --------------------------------------------------------------------
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  //
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  default clocking cb @(posedge clk);
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    output address;
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    output read;
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    input  readdata;
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    output write;
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    output writedata;
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    output byteenable;
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    input  waitrequest;
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    output arbiterlock;
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    input  readdatavalid;
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    output burstcount;
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    output resetrequest;
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    input   reset;
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    input   clk;
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  endclocking
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  // --------------------------------------------------------------------
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  //
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  assign amm_s.address      = address;
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  assign amm_s.read         = read;
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  assign readdata           = amm_s.readdata;
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  assign amm_s.write        = write;
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  assign amm_s.writedata    = writedata;
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  assign amm_s.byteenable   = byteenable;
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  assign waitrequest        = amm_s.waitrequest;
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  assign amm_s.arbiterlock  = arbiterlock;
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  assign readdatavalid      = amm_s.readdatavalid;
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  assign amm_s.burstcount   = burstcount;
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  assign amm_s.resetrequest = resetrequest;
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  // --------------------------------------------------------------------
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  //
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  function void
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    amm_default;
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    address       = 'bx;
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    arbiterlock   = 0;
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    burstcount    = 'bx;
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    byteenable    = 'bx;
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    read          = 0;
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    resetrequest  = 0;
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    write         = 0;
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    writedata     = 'bx;
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  endfunction: amm_default
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  // --------------------------------------------------------------------
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  //
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  function void
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    init;
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    amm_default();
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  endfunction: init
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  // --------------------------------------------------------------------
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  //
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  task
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    zero_cycle_delay;
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    ##0;
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  endtask: zero_cycle_delay
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  // --------------------------------------------------------------------
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  //
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  initial
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  begin
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    init();
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  end
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// --------------------------------------------------------------------
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//
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endinterface
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