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[/] [qaz_libs/] [trunk/] [avalon_lib/] [sim/] [src/] [amm_bfm/] [amm_slave_bfm_if.sv] - Blame information for rev 31

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1 31 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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interface
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  amm_slave_bfm_if
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  #(
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    A = 32, // address bus width
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    N = 8   // data bus width in bytes
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  )
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  (
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    amm_if amm_m,
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    output reset,
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    output clk
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  );
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        logic [(A-1):0]   address;
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        logic             read;
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        logic   [(8*N)-1:0] readdata;
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        logic             write;
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        logic   [(8*N)-1:0] writedata;
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        logic   [N-1:0]     byteenable;
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        logic             begintransfer;
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        logic             waitrequest;
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        logic             arbiterlock;
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        logic             readdatavalid;
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        logic   [6:0]       burstcount;
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        logic               beginbursttransfer;
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        logic               readyfordata;
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        logic               dataavailable;
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        logic               resetrequest;
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  // --------------------------------------------------------------------
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  //
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  default clocking cb @(posedge clk);
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    input   address;
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    input   read;
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    output  readdata;
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    input   write;
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    input   writedata;
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    input   byteenable;
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    input   begintransfer;
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    output  waitrequest;
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    input   arbiterlock;
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    output  readdatavalid;
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    input   burstcount;
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    input   beginbursttransfer;
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    output  readyfordata;
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    output  dataavailable;
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    output  resetrequest;
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    input   reset;
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    input   clk;
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  endclocking
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  // --------------------------------------------------------------------
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  //
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  assign address              = amm_m.address;
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  assign read                 = amm_m.read;
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  assign amm_m.readdata       = readdata;
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  assign write                = amm_m.write;
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  assign writedata            = amm_m.writedata;
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  assign byteenable           = amm_m.byteenable;
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  assign begintransfer        = amm_m.begintransfer;
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  assign amm_m.waitrequest    = waitrequest;
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  assign arbiterlock          = amm_m.arbiterlock;
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  assign amm_m.readdatavalid  = readdatavalid;
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  assign burstcount           = amm_m.burstcount;
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  assign beginbursttransfer   = amm_m.beginbursttransfer;
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  assign amm_m.readyfordata   = readyfordata;
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  assign amm_m.dataavailable  = dataavailable;
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  assign amm_m.resetrequest   = resetrequest;
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  // --------------------------------------------------------------------
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  //
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  function void
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    set_address_default;
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    waitrequest   = 1;
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  endfunction: set_address_default
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  // --------------------------------------------------------------------
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  //
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  function void
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    set_data_default;
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    readdata      = 'bx;
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    readdatavalid = 0;
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  endfunction: set_data_default
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  // --------------------------------------------------------------------
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  //
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  function void
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    init;
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    readyfordata  = 'bz;
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    dataavailable = 'bz;
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    resetrequest  = 'bz;
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    set_address_default();
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    set_data_default();
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  endfunction: init
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  // --------------------------------------------------------------------
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  //
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  task
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    zero_cycle_delay;
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    ##0;
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  endtask: zero_cycle_delay
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  // --------------------------------------------------------------------
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  //
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  import q_pkg::*;
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  import axi4_transaction_pkg::*;
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  // --------------------------------------------------------------------
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  //
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  class slave_write_transaction_class #(A = 32, N = 8, I = 1)
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    extends blocking_transmission_q_class #(axi4_transaction_class);
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    // --------------------------------------------------------------------
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    //
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    task automatic
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      transmit
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      (
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        ref T tr_h
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      );
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      ->this.start;
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      foreach(tr_h.payload_h.w[i])
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      begin
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        ##(tr_h.delay_h.next());
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        cb.waitrequest <= 0;
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        ##1;
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        wait(cb.write);
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        $display("^^^ %16.t | %m | AMM slave write  | %0d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
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        cb.waitrequest <= 1;
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      end
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      set_address_default();
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      set_data_default();
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      ->this.done;
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    endtask: transmit
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  // --------------------------------------------------------------------
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  //
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  endclass: slave_write_transaction_class
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  // --------------------------------------------------------------------
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  //
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  class slave_read_data_transaction_class #(A = 32, N = 8, I = 1)
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    extends blocking_transmission_q_class #(axi4_transaction_class);
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    // --------------------------------------------------------------------
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    //
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    task automatic
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      transmit
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      (
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        ref T tr_h
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      );
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      ->this.start;
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      foreach(tr_h.payload_h.w[i])
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      begin
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        if(tr_h.payload_h.w.size > 1)
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          ##1;  // slave burst response must be at lease one cycle after read address phase
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        ##(tr_h.delay_h.next());
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        cb.readdata <= tr_h.payload_h.w[i];
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        cb.readdatavalid <= 1;
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        ##1;
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        $display("^^^ %16.t | %m | AMM slave read data  | %0d of %0d | 0x%016x |", $time, i + 1, tr_h.payload_h.w.size, tr_h.payload_h.w[i]);
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        cb.readdatavalid <= 0;
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        cb.readdata <= 'bx;
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      end
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      set_data_default();
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      ->this.done;
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    endtask: transmit
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  // --------------------------------------------------------------------
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  //
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  endclass: slave_read_data_transaction_class
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  // --------------------------------------------------------------------
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  //
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  slave_read_data_transaction_class #(.A(A), .N(N), .I(1)) r_h;
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  class slave_read_address_transaction_class #(A = 32, N = 8, I = 1)
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    extends blocking_transmission_q_class #(axi4_transaction_class);
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    // --------------------------------------------------------------------
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    //
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    task automatic
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      transmit
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      (
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        ref T tr_h
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      );
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      ->this.start;
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      ##(tr_h.delay_h.next());
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      cb.waitrequest <= 0;
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      ##1;
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      wait(cb.read)
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      ##0;
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      $display("^^^ %16.t | %m | AMM slave read address | 0x%08x | %0d |", $time, tr_h.addr, tr_h.len + 1);
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      r_h.put(tr_h);
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      set_address_default();
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      ->this.done;
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    endtask: transmit
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  // --------------------------------------------------------------------
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  //
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  endclass: slave_read_address_transaction_class
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  // --------------------------------------------------------------------
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  //
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  slave_write_transaction_class #(.A(A), .N(N), .I(1)) w_h;
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  slave_read_address_transaction_class #(.A(A), .N(N), .I(1)) ar_h;
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  initial
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  begin
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    init();
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    w_h = new;
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    w_h.init();
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    ar_h = new;
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    ar_h.init();
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    r_h = new;
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    r_h.init();
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  end
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// --------------------------------------------------------------------
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//
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endinterface
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