OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [avalon_lib/] [sim/] [src/] [amm_monitor/] [altera_avalon_mm_monitor.sv] - Blame information for rev 31

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 31 qaztronic
// (C) 2001-2016 Intel Corporation. All rights reserved.
2
// Your use of Intel Corporation's design tools, logic functions and other
3
// software and tools, and its AMPP partner logic functions, and any output
4
// files any of the foregoing (including device programming or simulation
5
// files), and any associated documentation or information are expressly subject
6
// to the terms and conditions of the Intel Program License Subscription
7
// Agreement, Intel MegaCore Function License Agreement, or other applicable
8
// license agreement, including, without limitation, that your use is for the
9
// sole purpose of programming logic devices manufactured by Intel and sold by
10
// Intel or its authorized distributors.  Please refer to the applicable
11
// agreement for further details.
12
 
13
 
14
// $Id: //acds/rel/16.1/ip/sopc/components/verification/altera_avalon_mm_monitor_bfm/altera_avalon_mm_monitor.sv#1 $
15
// $Revision: #1 $
16
// $Date: 2016/08/07 $
17
//-----------------------------------------------------------------------------
18
// =head1 NAME
19
// altera_avalon_mm_monitor
20
// =head1 SYNOPSIS
21
// Bridge with Avalon Bus Protocol Assertion Checker
22
// The macro DISABLE_ALTERA_AVALON_SIM_SVA is defined to disable SVA processing
23
// The macro ALTERA_AVALON_SIM_MTI must be defined to enable transaction tracing
24
// The macro ENABLE_ALTERA_AVALON_TRANSACTION_RECORDING must be defined to
25
// enable transaction monitoring
26
//-----------------------------------------------------------------------------
27
 
28
`timescale 1ps / 1ps
29
 
30
module altera_avalon_mm_monitor(
31
                                clk,
32
                                reset,
33
 
34
                                avm_clken,
35
                                avs_clken,
36
 
37
                                avs_waitrequest,
38
                                avs_write,
39
                                avs_read,
40
                                avs_address,
41
                                avs_byteenable,
42
                                avs_burstcount,
43
                                avs_beginbursttransfer,
44
                                avs_begintransfer,
45
                                avs_writedata,
46
                                avs_readdata,
47
                                avs_readdatavalid,
48
                                avs_arbiterlock,
49
                                avs_lock,
50
                                avs_debugaccess,
51
                                avs_transactionid,
52
                                avs_readid,
53
                                avs_writeid,
54
                                avs_response,
55
                                avs_writeresponserequest,
56
                                avs_writeresponsevalid,
57
 
58
                                // deprecated signals
59
                                avs_readresponse,
60
                                avs_writeresponse,
61
                                avm_readresponse,
62
                                avm_writeresponse,
63
 
64
                                avm_waitrequest,
65
                                avm_write,
66
                                avm_read,
67
                                avm_address,
68
                                avm_byteenable,
69
                                avm_burstcount,
70
                                avm_beginbursttransfer,
71
                                avm_begintransfer,
72
                                avm_writedata,
73
                                avm_readdata,
74
                                avm_readdatavalid,
75
                                avm_arbiterlock,
76
                                avm_lock,
77
                                avm_debugaccess,
78
                                avm_transactionid,
79
                                avm_readid,
80
                                avm_writeid,
81
                                avm_response,
82
                                avm_writeresponserequest,
83
                                avm_writeresponsevalid
84
                                );
85
 
86
   // =head1 PARAMETERS
87
   parameter AV_ADDRESS_W               = 32;   // address width
88
   parameter AV_SYMBOL_W                = 8;    // default symbol is byte
89
   parameter AV_NUMSYMBOLS              = 4;    // number of symbols per word
90
   parameter AV_BURSTCOUNT_W            = 3;    // burst port width
91
 
92
   // deprecated parameter
93
   parameter AV_WRITERESPONSE_W         = 8;
94
   parameter AV_READRESPONSE_W          = 8;
95
 
96
   parameter AV_CONSTANT_BURST_BEHAVIOR = 1;    // Address, burstcount, transactionid and
97
                                                // avm_writeresponserequest need to be held constant
98
                                                // in burst transaction
99
   parameter AV_BURST_LINEWRAP          = 0;    // line wrapping addr is set to 1
100
   parameter AV_BURST_BNDR_ONLY         = 0;    // addr is multiple of burst size
101
   parameter REGISTER_WAITREQUEST       = 0;    // Waitrequest is registered at the slave
102
   parameter AV_MAX_PENDING_READS       = 1;    // maximum pending read transfer count
103
   parameter AV_MAX_PENDING_WRITES      = 0;    // maximum pending write transfer count
104
   parameter AV_FIX_READ_LATENCY        = 0;    // fixed read latency in cycles
105
 
106
   parameter USE_READ                   = 1;    // use read port
107
   parameter USE_WRITE                  = 1;    // use write port
108
   parameter USE_ADDRESS                = 1;    // use address port
109
   parameter USE_BYTE_ENABLE            = 1;    // use byteenable port
110
   parameter USE_BURSTCOUNT             = 0;    // use burstcount port
111
   parameter USE_READ_DATA              = 1;    // use readdata port
112
   parameter USE_READ_DATA_VALID        = 1;    // use readdatavalid port
113
   parameter USE_WRITE_DATA             = 1;    // use writedata port
114
   parameter USE_BEGIN_TRANSFER         = 0;    // use begintransfer port
115
   parameter USE_BEGIN_BURST_TRANSFER   = 0;    // use begintbursttransfer port
116
   parameter USE_WAIT_REQUEST           = 1;    // use waitrequest port
117
   parameter USE_ARBITERLOCK            = 0;    // Use arbiterlock pin on interface
118
   parameter USE_LOCK                   = 0;    // Use lock pin on interface
119
   parameter USE_DEBUGACCESS            = 0;    // Use debugaccess pin on interface
120
   parameter USE_TRANSACTIONID          = 0;    // Use transactionid interface pin
121
   parameter USE_WRITERESPONSE          = 0;    // Use write response interface pins
122
   parameter USE_READRESPONSE           = 0;    // Use read response interface pins
123
   parameter USE_CLKEN                  = 0;    // Use NTCM interface pins
124
 
125
   parameter AV_READ_TIMEOUT            = 100;  // timeout period for read transfer
126
   parameter AV_WRITE_TIMEOUT           = 100;  // timeout period for write burst transfer
127
   parameter AV_WAITREQUEST_TIMEOUT     = 1024; // timeout period for continuous waitrequest
128
   parameter AV_MAX_READ_LATENCY        = 100;  // maximum read latency cycle for coverage
129
   parameter AV_MAX_WAITREQUESTED_READ  = 100;  // maximum waitrequested read cycle for coverage
130
   parameter AV_MAX_WAITREQUESTED_WRITE = 100;  // maximum waitrequested write cycle for coverage
131
   parameter AV_MAX_CONTINUOUS_READ          = 5;   // maximum continuous read cycle for coverage
132
   parameter AV_MAX_CONTINUOUS_WRITE         = 5;   // maximum continuous write cycle for coverage
133
   parameter AV_MAX_CONTINUOUS_WAITREQUEST   = 5;   // maximum continuous waitrequest cycle for coverage
134
   parameter AV_MAX_CONTINUOUS_READDATAVALID = 5;   // maximum continuous readdatavalid cycle for coverage
135
   parameter string SLAVE_ADDRESS_TYPE = "SYMBOLS";   // Set slave interface address type, {SYMBOLS, WORDS}
136
   parameter string MASTER_ADDRESS_TYPE = "SYMBOLS";  // Set master interface address type, {SYMBOLS, WORDS}
137
 
138
   parameter AV_READ_WAIT_TIME         = 0;  // Fixed wait time cycles when
139
   parameter AV_WRITE_WAIT_TIME        = 0;  // USE_WAIT_REQUEST is 0
140
 
141
   parameter AV_REGISTERINCOMINGSIGNALS = 0;  // Indicate that waitrequest is come from register
142
   parameter VHDL_ID                    = 0;   // VHDL BFM ID number
143
   parameter PRINT_HELLO                = 1;  // To enable the printing of __hello message
144
   parameter STORE_COMMAND            = 1; // Store commands inside command queue
145
   parameter STORE_RESPONSE           = 1; // Store responses inside response queue
146
 
147
   localparam AV_DATA_W = AV_SYMBOL_W * AV_NUMSYMBOLS;
148
   localparam AV_MAX_BURST = USE_BURSTCOUNT ? 2**(lindex(AV_BURSTCOUNT_W)) : 1;
149
   localparam INT_WIDTH = 32;
150
   localparam AV_TRANSACTIONID_W = 8;
151
 
152
   localparam AV_SLAVE_ADDRESS_W = (SLAVE_ADDRESS_TYPE != MASTER_ADDRESS_TYPE)? (AV_ADDRESS_W - log2(AV_NUMSYMBOLS)):AV_ADDRESS_W;
153
 
154
   localparam TAP_W = 1 +                                                  // clken
155
                      1 +                                                  // arbiterlock
156
                      1 +                                                  // lock
157
                      1 +                                                  // debugaccess
158
                      ((AV_TRANSACTIONID_W == 0)? 1:AV_TRANSACTIONID_W) +  // transactionid
159
                      ((AV_TRANSACTIONID_W == 0)? 1:AV_TRANSACTIONID_W) +  // readid
160
                      ((AV_TRANSACTIONID_W == 0)? 1:AV_TRANSACTIONID_W) +  // writeid
161
                      2 +                                                  // response
162
                      1 +                                                  // writeresponserequest
163
                      1 +                                                  // writeresponsevalid
164
                      1 +                                                  // waitrequest
165
                      1 +                                                  // readdatavalid
166
                      ((AV_DATA_W == 0)? 1:AV_DATA_W) +                    // readdata
167
                      1 +                                                  // write
168
                      1 +                                                  // read
169
                      ((AV_ADDRESS_W == 0)? 1:AV_ADDRESS_W) +              // address
170
                      ((AV_NUMSYMBOLS == 0)? 1:AV_NUMSYMBOLS) +            // byteenable
171
                      ((AV_BURSTCOUNT_W == 0)? 1:AV_BURSTCOUNT_W) +        // burstcount
172
                      1 +                                                  // beginbursttransfer
173
                      1 +                                                  // begintransfer
174
                      ((AV_DATA_W == 0)? 1:AV_DATA_W);                     // writedata
175
 
176
   function int lindex;
177
      // returns the left index for a vector having a declared width
178
      // when width is 0, then the left index is set to 0 rather than -1
179
      input [31:0] width;
180
      lindex = (width > 0) ? (width-1) : 0;
181
   endfunction
182
 
183
   // =head1 PINS
184
   // =head2 Clock Interface
185
   input                                           clk;
186
   input                                           reset;
187
 
188
   // =head2 Tightly Coupled Memory Interface
189
   output                                          avm_clken;
190
   input                                           avs_clken;
191
 
192
   // =head2 Avalon Master Interface
193
   input                                           avm_waitrequest;
194
   input                                           avm_readdatavalid;
195
   input  [lindex(AV_SYMBOL_W * AV_NUMSYMBOLS):0]  avm_readdata;
196
   output                                          avm_write;
197
   output                                          avm_read;
198
   output [lindex(AV_ADDRESS_W):0]                 avm_address;
199
   output [lindex(AV_NUMSYMBOLS):0]                avm_byteenable;
200
   output [lindex(AV_BURSTCOUNT_W):0]              avm_burstcount;
201
   output                                          avm_beginbursttransfer;
202
   output                                          avm_begintransfer;
203
   output [lindex(AV_SYMBOL_W * AV_NUMSYMBOLS):0]  avm_writedata;
204
   output                                          avm_arbiterlock;
205
   output                                          avm_lock;
206
   output                                          avm_debugaccess;
207
 
208
   output [lindex(AV_TRANSACTIONID_W):0]           avm_transactionid;
209
   input  [lindex(AV_TRANSACTIONID_W):0]           avm_readid;
210
   input  [lindex(AV_TRANSACTIONID_W):0]           avm_writeid;
211
   input  [1:0]                                    avm_response;
212
   output                                          avm_writeresponserequest;
213
   input                                           avm_writeresponsevalid;
214
 
215
   // deprecated
216
   input  [lindex(AV_READRESPONSE_W):0]            avm_readresponse;
217
   input  [lindex(AV_WRITERESPONSE_W):0]           avm_writeresponse;
218
 
219
   // =head2 Avalon Slave Interface
220
   output                                          avs_waitrequest;
221
   output                                          avs_readdatavalid;
222
   output [lindex(AV_SYMBOL_W * AV_NUMSYMBOLS):0]  avs_readdata;
223
   input                                           avs_write;
224
   input                                           avs_read;
225
   input  [lindex(AV_SLAVE_ADDRESS_W):0]           avs_address;
226
   input  [lindex(AV_NUMSYMBOLS):0]                avs_byteenable;
227
   input  [lindex(AV_BURSTCOUNT_W):0]              avs_burstcount;
228
   input                                           avs_beginbursttransfer;
229
   input                                           avs_begintransfer;
230
   input  [lindex(AV_SYMBOL_W * AV_NUMSYMBOLS):0]  avs_writedata;
231
   input                                           avs_arbiterlock;
232
   input                                           avs_lock;
233
   input                                           avs_debugaccess;
234
 
235
   input  [lindex(AV_TRANSACTIONID_W):0]           avs_transactionid;
236
   output [lindex(AV_TRANSACTIONID_W):0]           avs_readid;
237
   output [lindex(AV_TRANSACTIONID_W):0]           avs_writeid;
238
   output [1:0]                                    avs_response;
239
   input                                           avs_writeresponserequest;
240
   output                                          avs_writeresponsevalid;
241
 
242
   // deprecated
243
   output [lindex(AV_READRESPONSE_W):0]            avs_readresponse;
244
   output [lindex(AV_WRITERESPONSE_W):0]           avs_writeresponse;
245
 
246
   logic                                           avm_clken;
247
   logic                                           avs_clken;
248
 
249
   logic                                           avm_waitrequest;
250
   logic                                           avm_readdatavalid;
251
   logic  [lindex(AV_SYMBOL_W * AV_NUMSYMBOLS):0]  avm_readdata;
252
   logic                                           avm_write;
253
   logic                                           avm_read;
254
   logic [lindex(AV_ADDRESS_W):0]                  avm_address;
255
   logic [lindex(AV_NUMSYMBOLS):0]                 avm_byteenable;
256
   logic [lindex(AV_BURSTCOUNT_W):0]               avm_burstcount;
257
   logic                                           avm_beginbursttransfer;
258
   logic                                           avm_begintransfer;
259
   logic [lindex(AV_SYMBOL_W * AV_NUMSYMBOLS):0]   avm_writedata;
260
   logic                                           avm_arbiterlock;
261
   logic                                           avm_lock;
262
   logic                                           avm_debugaccess;
263
 
264
   logic [lindex(AV_TRANSACTIONID_W):0]            avm_transactionid;
265
   logic [lindex(AV_TRANSACTIONID_W):0]            avm_readid;
266
   logic [lindex(AV_TRANSACTIONID_W):0]            avm_writeid;
267
   logic [1:0]                                     avm_response;
268
   logic                                           avm_writeresponserequest;
269
   logic                                           avm_writeresponsevalid;
270
 
271
   // deprecated
272
   logic [lindex(AV_READRESPONSE_W):0]             avm_readresponse;
273
   logic [lindex(AV_WRITERESPONSE_W):0]            avm_writeresponse;
274
 
275
 
276
   logic                                           avs_waitrequest;
277
   logic                                           avs_readdatavalid;
278
   logic  [lindex(AV_SYMBOL_W * AV_NUMSYMBOLS):0]  avs_readdata;
279
   logic                                           avs_write;
280
   logic                                           avs_read;
281
   logic [lindex(AV_SLAVE_ADDRESS_W):0]            avs_address;
282
   logic [lindex(AV_NUMSYMBOLS):0]                 avs_byteenable;
283
   logic [lindex(AV_BURSTCOUNT_W):0]               avs_burstcount;
284
   logic                                           avs_beginbursttransfer;
285
   logic                                           avs_begintransfer;
286
   logic [lindex(AV_SYMBOL_W * AV_NUMSYMBOLS):0]   avs_writedata;
287
   logic                                           avs_arbiterlock;
288
   logic                                           avs_lock;
289
   logic                                           avs_debugaccess;
290
 
291
   logic [lindex(AV_TRANSACTIONID_W):0]            avs_transactionid;
292
   logic [lindex(AV_TRANSACTIONID_W):0]            avs_readid;
293
   logic [lindex(AV_TRANSACTIONID_W):0]            avs_writeid;
294
   logic [1:0]                                     avs_response;
295
   logic                                           avs_writeresponserequest;
296
   logic                                           avs_writeresponsevalid;
297
 
298
   // deprecated
299
   logic [lindex(AV_READRESPONSE_W):0]             avs_readresponse;
300
   logic [lindex(AV_WRITERESPONSE_W):0]            avs_writeresponse;
301
 
302
   logic [lindex(TAP_W):0]                         tap;
303
 
304
   logic [31:0] read_wait_time = 0;
305
   logic [31:0] write_wait_time = 0;
306
   logic local_avs_waitrequest;
307
 
308
   bit master_slave_address_type_mismatch;
309
 
310
   // Use SLAVE_ADDRESS_TYPE/MASTER_ADDRESS_TYPE inside always_comb block will causing an warning
311
   initial begin
312
      master_slave_address_type_mismatch = (SLAVE_ADDRESS_TYPE != MASTER_ADDRESS_TYPE);
313
   end
314
 
315
   //--------------------------------------------------------------------------
316
   // =head1 DESCRIPTION
317
   // The component acts as a simple repeater or bridge with Avalon bus
318
   // signals passed through from the slave to master interface.
319
   // The instantiated altera_avalon_mm_monitor snoops all passing Avalon
320
   // bus signals and performs assertion checking and measures coverage on
321
   // Avalon Memory Mapped protocol properties.
322
   // =cut
323
   //--------------------------------------------------------------------------
324
 
325
   always_comb begin
326
      // repeater
327
      avm_clken                     <= avs_clken;
328
 
329
      if (USE_WAIT_REQUEST == 0) begin
330
         avs_waitrequest            <= local_avs_waitrequest;
331
      end else begin
332
         avs_waitrequest            <= avm_waitrequest;
333
      end
334
 
335
      avs_readdatavalid             <= avm_readdatavalid;
336
      avs_readdata                  <= avm_readdata;
337
 
338
      avm_write                     <= avs_write;
339
      avm_read                      <= avs_read;
340
      if (master_slave_address_type_mismatch)
341
         avm_address                <= address_shift(avs_address);
342
      else
343
         avm_address                <= avs_address;
344
      avm_byteenable                <= avs_byteenable;
345
      avm_burstcount                <= avs_burstcount;
346
      avm_beginbursttransfer        <= avs_beginbursttransfer;
347
      avm_begintransfer             <= avs_begintransfer;
348
      avm_writedata                 <= avs_writedata;
349
 
350
      avm_arbiterlock               <= avs_arbiterlock;
351
      avm_lock                      <= avs_lock;
352
      avm_debugaccess               <= avs_debugaccess;
353
      avm_transactionid             <= avs_transactionid;
354
      avs_readid                    <= avm_readid;
355
      avs_writeid                   <= avm_writeid;
356
      avm_writeresponserequest      <= avs_writeresponserequest;
357
      avs_writeresponsevalid        <= avm_writeresponsevalid;
358
      avs_response                  <= avm_response;
359
 
360
      // snoop bus for assertion and coverage checking
361
      if (master_slave_address_type_mismatch) begin
362
         tap <=  {
363
                 avs_clken,
364
                 avs_arbiterlock,
365
                 avs_lock,
366
                 avs_debugaccess,
367
                 avs_transactionid,
368
                 avm_readid,
369
                 avm_writeid,
370
                 avm_response,
371
                 avs_writeresponserequest,
372
                 avm_writeresponsevalid,
373
 
374
                 (USE_WAIT_REQUEST == 0)? local_avs_waitrequest:avm_waitrequest,
375
                 avm_readdatavalid,
376
                 avm_readdata,
377
 
378
                 avs_write,
379
                 avs_read,
380
                 address_shift(avs_address),
381
                 avs_byteenable,
382
                 avs_burstcount,
383
                 avs_beginbursttransfer,
384
                 avs_begintransfer,
385
                 avs_writedata
386
                 };
387
      end else begin
388
         tap <=  {
389
                 avs_clken,
390
                 avs_arbiterlock,
391
                 avs_lock,
392
                 avs_debugaccess,
393
                 avs_transactionid,
394
                 avm_readid,
395
                 avm_writeid,
396
                 avm_response,
397
                 avs_writeresponserequest,
398
                 avm_writeresponsevalid,
399
 
400
                 (USE_WAIT_REQUEST == 0)? local_avs_waitrequest:avm_waitrequest,
401
                 avm_readdatavalid,
402
                 avm_readdata,
403
 
404
                 avs_write,
405
                 avs_read,
406
                 avs_address,
407
                 avs_byteenable,
408
                 avs_burstcount,
409
                 avs_beginbursttransfer,
410
                 avs_begintransfer,
411
                 avs_writedata
412
                 };
413
      end
414
   end
415
 
416
   //--------------------------------------------------------------------------
417
   // =head1 ALTERA_AVALON_MM_MONITOR_ASSERTION
418
   // This module implements Avalon MM protocol assertion checking for
419
   // simulation.
420
   // Component name = monitor_assertion.
421
   // =cut
422
   //--------------------------------------------------------------------------
423
   altera_avalon_mm_monitor_assertion
424
     #(
425
       .AV_ADDRESS_W               (AV_ADDRESS_W),
426
       .AV_SYMBOL_W                (AV_SYMBOL_W),
427
       .AV_NUMSYMBOLS              (AV_NUMSYMBOLS),
428
       .AV_BURSTCOUNT_W            (AV_BURSTCOUNT_W),
429
       .AV_CONSTANT_BURST_BEHAVIOR (AV_CONSTANT_BURST_BEHAVIOR),
430
       .AV_BURST_LINEWRAP          (AV_BURST_LINEWRAP),
431
       .AV_BURST_BNDR_ONLY         (AV_BURST_BNDR_ONLY),
432
       .AV_MAX_PENDING_READS       (AV_MAX_PENDING_READS),
433
       .AV_MAX_PENDING_WRITES      (AV_MAX_PENDING_WRITES),
434
       .AV_FIX_READ_LATENCY        (AV_FIX_READ_LATENCY),
435
 
436
       .REGISTER_WAITREQUEST       (REGISTER_WAITREQUEST),
437
 
438
       .USE_READ                   (USE_READ),
439
       .USE_WRITE                  (USE_WRITE),
440
       .USE_ADDRESS                (USE_ADDRESS),
441
       .USE_BYTE_ENABLE            (USE_BYTE_ENABLE),
442
       .USE_BURSTCOUNT             (USE_BURSTCOUNT),
443
       .USE_READ_DATA              (USE_READ_DATA),
444
       .USE_READ_DATA_VALID        (USE_READ_DATA_VALID),
445
       .USE_WRITE_DATA             (USE_WRITE_DATA),
446
       .USE_BEGIN_TRANSFER         (USE_BEGIN_TRANSFER),
447
       .USE_BEGIN_BURST_TRANSFER   (USE_BEGIN_BURST_TRANSFER),
448
       .USE_WAIT_REQUEST           (USE_WAIT_REQUEST),
449
 
450
       .USE_ARBITERLOCK            (USE_ARBITERLOCK),
451
       .USE_LOCK                   (USE_LOCK),
452
       .USE_DEBUGACCESS            (USE_DEBUGACCESS),
453
       .USE_TRANSACTIONID          (USE_TRANSACTIONID),
454
       .USE_WRITERESPONSE          (USE_WRITERESPONSE),
455
       .USE_READRESPONSE           (USE_READRESPONSE),
456
       .USE_CLKEN                  (USE_CLKEN),
457
 
458
       .AV_READ_TIMEOUT            (AV_READ_TIMEOUT),
459
       .AV_WRITE_TIMEOUT           (AV_WRITE_TIMEOUT),
460
       .AV_WAITREQUEST_TIMEOUT     (AV_WAITREQUEST_TIMEOUT),
461
       .AV_READ_WAIT_TIME          (AV_READ_WAIT_TIME),
462
       .AV_WRITE_WAIT_TIME         (AV_WRITE_WAIT_TIME),
463
       .AV_REGISTERINCOMINGSIGNALS (AV_REGISTERINCOMINGSIGNALS),
464
       .SLAVE_ADDRESS_TYPE         (SLAVE_ADDRESS_TYPE),
465
       .MASTER_ADDRESS_TYPE        (MASTER_ADDRESS_TYPE)
466
      )
467
     master_assertion (
468
                      .clk         (clk),
469
                      .reset       (reset),
470
                      .tap         (tap)
471
                      );
472
 
473
   //--------------------------------------------------------------------------
474
   // =head1 ALTERA_AVALON_MM_MONITOR_COVERAGE
475
   // This module implements Avalon MM protocol coverage for simulation.
476
   // Component name = monitor_coverage.
477
   // =cut
478
   //--------------------------------------------------------------------------
479
   altera_avalon_mm_monitor_coverage
480
     #(
481
       .AV_ADDRESS_W               (AV_ADDRESS_W),
482
       .AV_SYMBOL_W                (AV_SYMBOL_W),
483
       .AV_NUMSYMBOLS              (AV_NUMSYMBOLS),
484
       .AV_BURSTCOUNT_W            (AV_BURSTCOUNT_W),
485
       .AV_BURST_LINEWRAP          (AV_BURST_LINEWRAP),
486
       .AV_BURST_BNDR_ONLY         (AV_BURST_BNDR_ONLY),
487
       .AV_MAX_PENDING_READS       (AV_MAX_PENDING_READS),
488
       .AV_MAX_PENDING_WRITES      (AV_MAX_PENDING_WRITES),
489
       .AV_FIX_READ_LATENCY        (AV_FIX_READ_LATENCY),
490
 
491
       .REGISTER_WAITREQUEST       (REGISTER_WAITREQUEST),
492
 
493
       .USE_READ                   (USE_READ),
494
       .USE_WRITE                  (USE_WRITE),
495
       .USE_ADDRESS                (USE_ADDRESS),
496
       .USE_BYTE_ENABLE            (USE_BYTE_ENABLE),
497
       .USE_BURSTCOUNT             (USE_BURSTCOUNT),
498
       .USE_READ_DATA              (USE_READ_DATA),
499
       .USE_READ_DATA_VALID        (USE_READ_DATA_VALID),
500
       .USE_WRITE_DATA             (USE_WRITE_DATA),
501
       .USE_BEGIN_TRANSFER         (USE_BEGIN_TRANSFER),
502
       .USE_BEGIN_BURST_TRANSFER   (USE_BEGIN_BURST_TRANSFER),
503
       .USE_WAIT_REQUEST           (USE_WAIT_REQUEST),
504
       .USE_CLKEN                  (USE_CLKEN),
505
 
506
       .USE_ARBITERLOCK            (USE_ARBITERLOCK),
507
       .USE_LOCK                   (USE_LOCK),
508
       .USE_DEBUGACCESS            (USE_DEBUGACCESS),
509
       .USE_TRANSACTIONID          (USE_TRANSACTIONID),
510
       .USE_WRITERESPONSE          (USE_WRITERESPONSE),
511
       .USE_READRESPONSE           (USE_READRESPONSE),
512
 
513
       .AV_MAX_READ_LATENCY        (AV_MAX_READ_LATENCY),
514
       .AV_MAX_WAITREQUESTED_READ  (AV_MAX_WAITREQUESTED_READ),
515
       .AV_MAX_WAITREQUESTED_WRITE (AV_MAX_WAITREQUESTED_WRITE),
516
       .AV_MAX_CONTINUOUS_READ     (AV_MAX_CONTINUOUS_READ),
517
       .AV_MAX_CONTINUOUS_WRITE    (AV_MAX_CONTINUOUS_WRITE),
518
       .AV_MAX_CONTINUOUS_WAITREQUEST     (AV_MAX_CONTINUOUS_WAITREQUEST),
519
       .AV_MAX_CONTINUOUS_READDATAVALID   (AV_MAX_CONTINUOUS_READDATAVALID),
520
       .AV_READ_WAIT_TIME          (AV_READ_WAIT_TIME),
521
       .AV_WRITE_WAIT_TIME         (AV_WRITE_WAIT_TIME)
522
      )
523
     master_coverage(
524
                    .clk         (clk),
525
                    .reset       (reset),
526
                    .tap         (tap)
527
                    );
528
 
529
   //--------------------------------------------------------------------------
530
   // =head1 ALTERA_AVALON_MM_MONITOR_TRANSACTIONS
531
   // This module implements Avalon-MM the transaction recorder.
532
   // =cut
533
   //--------------------------------------------------------------------------
534
   `ifdef ENABLE_ALTERA_AVALON_TRANSACTION_RECORDING
535
   altera_avalon_mm_monitor_transactions
536
     #(
537
       .AV_ADDRESS_W               (AV_ADDRESS_W),
538
       .AV_SYMBOL_W                (AV_SYMBOL_W),
539
       .AV_NUMSYMBOLS              (AV_NUMSYMBOLS),
540
       .AV_BURSTCOUNT_W            (AV_BURSTCOUNT_W),
541
       .AV_BURST_LINEWRAP          (AV_BURST_LINEWRAP),
542
       .AV_BURST_BNDR_ONLY         (AV_BURST_BNDR_ONLY),
543
       .AV_MAX_PENDING_READS       (AV_MAX_PENDING_READS),
544
       .AV_MAX_PENDING_WRITES      (AV_MAX_PENDING_WRITES),
545
       .AV_FIX_READ_LATENCY        (AV_FIX_READ_LATENCY),
546
 
547
       // deprecated
548
       // deprecated parameter
549
       .AV_WRITERESPONSE_W         (AV_WRITERESPONSE_W),
550
       .AV_READRESPONSE_W          (AV_READRESPONSE_W),
551
 
552
       .REGISTER_WAITREQUEST       (REGISTER_WAITREQUEST),
553
 
554
       .USE_READ                   (USE_READ),
555
       .USE_WRITE                  (USE_WRITE),
556
       .USE_ADDRESS                (USE_ADDRESS),
557
       .USE_BYTE_ENABLE            (USE_BYTE_ENABLE),
558
       .USE_BURSTCOUNT             (USE_BURSTCOUNT),
559
       .USE_READ_DATA              (USE_READ_DATA),
560
       .USE_READ_DATA_VALID        (USE_READ_DATA_VALID),
561
       .USE_WRITE_DATA             (USE_WRITE_DATA),
562
       .USE_BEGIN_TRANSFER         (USE_BEGIN_TRANSFER),
563
       .USE_BEGIN_BURST_TRANSFER   (USE_BEGIN_BURST_TRANSFER),
564
       .USE_WAIT_REQUEST           (USE_WAIT_REQUEST),
565
       .USE_CLKEN                  (USE_CLKEN),
566
 
567
       .USE_ARBITERLOCK            (USE_ARBITERLOCK),
568
       .USE_LOCK                   (USE_LOCK),
569
       .USE_DEBUGACCESS            (USE_DEBUGACCESS),
570
       .USE_TRANSACTIONID          (USE_TRANSACTIONID),
571
       .USE_WRITERESPONSE          (USE_WRITERESPONSE),
572
       .USE_READRESPONSE           (USE_READRESPONSE),
573
 
574
       .AV_READ_WAIT_TIME          (AV_READ_WAIT_TIME),
575
       .AV_WRITE_WAIT_TIME         (AV_WRITE_WAIT_TIME),
576
       .STORE_RESPONSE             (STORE_RESPONSE),
577
       .STORE_COMMAND              (STORE_COMMAND)
578
      )
579
     monitor_trans(
580
                    .clk         (clk),
581
                    .reset       (reset),
582
                    .tap         (tap)
583
                    );
584
   `endif
585
 
586
   // synthesis translate_off
587
   import verbosity_pkg::*;
588
   import avalon_mm_pkg::*;
589
 
590
   typedef bit [lindex(AV_ADDRESS_W):0]                    AvalonAddress_t;
591
   typedef bit [lindex(AV_BURSTCOUNT_W):0]                 AvalonBurstCount_t;
592
   typedef bit [AV_MAX_BURST-1:0][AV_DATA_W-1:0]     AvalonData_t;
593
   typedef bit [AV_MAX_BURST-1:0][AV_NUMSYMBOLS-1:0] AvalonByteEnable_t;
594
   typedef bit [AV_MAX_BURST-1:0][INT_WIDTH-1:0]     AvalonLatency_t;
595
 
596
   typedef struct packed {
597
                          Request_t                  request;
598
                          AvalonAddress_t            address;     // start address
599
                          AvalonBurstCount_t         burst_count; // burst length
600
                          AvalonData_t               data;        // write data
601
                          AvalonByteEnable_t         byte_enable; // hot encoded
602
                          int                        burst_cycle;
603
                         } SlaveCommand_t;
604
 
605
   typedef struct packed {
606
                          Request_t                  request;
607
                          AvalonAddress_t            address;     // start addr
608
                          AvalonBurstCount_t         burst_count; // burst length
609
                          AvalonData_t               data;        // read data
610
                          AvalonLatency_t            read_latency;
611
                          AvalonLatency_t            wait_latency;
612
                         } MasterResponse_t;
613
 
614
 
615
   //--------------------------------------------------------------------------
616
   // =head1 Public Methods API
617
   // This section describes the public methods in the application programming
618
   // interface (API). In this case the application program is the test bench
619
   // which instantiates and controls and queries state of this component.
620
   // Test programs must only use these public access methods and events to
621
   // communicate with this BFM component. The API and the module pins
622
   // are the only interfaces in this component that are guaranteed to be
623
   // stable. The API will be maintained for the life of the product.
624
   // While we cannot prevent a test program from directly accessing internal
625
   // tasks, functions, or data private to the BFM, there is no guarantee that
626
   // these will be present in the future. In fact, it is best for the user
627
   // to assume that the underlying implementation of this component can
628
   // and will change.
629
   //--------------------------------------------------------------------------
630
 
631
   function automatic string get_version();  // public
632
      // Return component version as a string of three integers separated by periods.
633
      // For example, version 9.1 sp1 is encoded as "9.1.1".
634
      string ret_version = "16.1";
635
      return ret_version;
636
   endfunction
637
 
638
   // =cut
639
   //--------------------------------------------------------------------------
640
   // Public API Method(s) - end
641
   //--------------------------------------------------------------------------
642
 
643
   function automatic void hello();
644
      // introduction message to the console
645
      string message;
646
      $sformat(message, "%m: - Hello from altera_avalon_mm_monitor");
647
      print(VERBOSITY_INFO, message);
648
      `ifdef DISABLE_ALTERA_AVALON_SIM_SVA
649
      $sformat(message, "%m: -   Assertions disabled (DISABLE_ALTERA_AVALON_SIM_SVA defined)");
650
      `else
651
      $sformat(message, "%m: -   Assertions enabled (DISABLE_ALTERA_AVALON_SIM_SVA undefined)");
652
      `endif
653
      print(VERBOSITY_INFO, message);
654
      `ifdef ALTERA_AVALON_SIM_MTI
655
      $sformat(message, "%m: -   Transaction tracing enabled (ALTERA_AVALON_SIM_MTI defined)");
656
      `else
657
      $sformat(message, "%m: -   Transaction tracing disabled (ALTERA_AVALON_SIM_MTI undefined)");
658
      `endif
659
      print(VERBOSITY_INFO, message);
660
      $sformat(message, "%m: -   $Revision: #1 $");
661
      print(VERBOSITY_INFO, message);
662
      $sformat(message, "%m: -   $Date: 2016/08/07 $");
663
      print(VERBOSITY_INFO, message);
664
      print_divider(VERBOSITY_INFO);
665
   endfunction
666
 
667
   //--------------------------------------------------------------------------
668
   // The Mentor QuestaSim simulation transaction tracing feature is supported
669
   // by enabling the macro: +define+ALTERA_AVALON_SIM_MTI in CLI
670
   SlaveCommand_t    current_command;
671
   MasterResponse_t  completed_response;
672
 
673
   int               command_trans;
674
   int               command_trans_stream;
675
 
676
   int               addr_offset = 0;
677
   bit               burst_mode = 0;
678
   int               command_counter = 0;
679
   int               response_counter = 0;
680
   int               clock_counter = 0;
681
   string            message = "*unitialized*";
682
 
683
   event             signal_fatal_error;
684
   event             command;
685
   event             response;
686
 
687
   function automatic void init_transaction_recording();
688
      `ifdef ALTERA_AVALON_SIM_MTI
689
      command_trans_stream =
690
         $create_transaction_stream("avalon_mm_monitor_bfm_cmd");
691
      `endif
692
   endfunction
693
 
694
   function automatic void begin_record_command_trans();
695
      `ifdef ALTERA_AVALON_SIM_MTI
696
         command_trans = $begin_transaction(command_trans_stream, "Command");
697
      `endif
698
   endfunction
699
 
700
   function automatic void end_record_command_trans();
701
      `ifdef ALTERA_AVALON_SIM_MTI
702
      string field;
703
      if (!reset) begin
704
         $add_attribute(command_trans, current_command.request, "request");
705
         $add_attribute(command_trans, current_command.address, "address");
706
         $add_attribute(command_trans, current_command.burst_count, "burst_count");
707
         if (current_command.request == REQ_WRITE) begin
708
            for (int i=0; i
709
               $sformat(field, "data_cycle_%0d", i);
710
               $add_attribute(command_trans, current_command.data[i], field);
711
               $sformat(field, "byte_enable_cycle_%0d", i);
712
               $add_attribute(command_trans, current_command.byte_enable[i], field);
713
            end
714
         end
715
         $end_transaction(command_trans);
716
         $free_transaction(command_trans);
717
      end
718
      `endif
719
   endfunction
720
 
721
   //--------------------------------------------------------------------------
722
 
723
   initial begin
724
      // $vcdpluson;  // for debugging with DVE
725
      if (PRINT_HELLO)
726
      hello();
727
      init_transaction_recording();
728
   end
729
 
730
   //--------------------------------------------------------------------------
731
   always @(posedge clk) clock_counter++;
732
   always @(command) command_counter++;
733
   always @(response) response_counter++;
734
 
735
   always @(signal_fatal_error) begin
736
      $sformat(message, "%m: Terminate simulation.");
737
      print(VERBOSITY_FAILURE, message);
738
      abort_simulation();
739
   end
740
 
741
   always @(posedge clk) begin
742
      fork: monitor
743
      begin
744
         #1 monitor_command();
745
         begin_record_command_trans();
746
      end
747
      begin
748
         @(posedge clk);
749
         end_record_command_trans();
750
      end
751
      join_any;
752
   end
753
 
754
   task monitor_command();
755
      current_command.address = avm_address;
756
      current_command.burst_count = avm_burstcount;
757
      if (avm_read && avm_write) begin
758
         current_command.address = avm_address;
759
         $sformat(message, "%m: Error - both write and read active, address: %0d",
760
                  current_command.address);
761
         print(VERBOSITY_FAILURE, message);
762
      end else if (avm_write) begin
763
         if (avm_beginbursttransfer) begin
764
            current_command = '0;
765
            addr_offset = 0;
766
            burst_mode = 1;
767
         end else if (burst_mode) begin
768
            if (addr_offset == avm_burstcount-1) begin
769
               burst_mode = 0;
770
               addr_offset = 0;
771
            end else begin
772
               addr_offset++;
773
            end
774
         end else begin
775
            current_command = '0;
776
            burst_mode = 0;
777
            addr_offset = 0;
778
         end
779
         current_command.request = REQ_WRITE;
780
         current_command.data[addr_offset] = avm_writedata;
781
         current_command.byte_enable[addr_offset] = avm_byteenable;
782
         current_command.burst_cycle = addr_offset;
783
         ->command;
784
      end else if (avm_read) begin
785
         current_command = '0;
786
         burst_mode = 0;
787
         addr_offset = 0;
788
         current_command.request = REQ_READ;
789
         // according to the Avalon spec, we expect that the master does
790
         // not drive writedata and byteenable during read request, but
791
         // this behavior may be violated in custom components
792
         current_command.data = avm_writedata;
793
         current_command.byte_enable = avm_byteenable;
794
      end
795
   endtask
796
 
797
   always @(posedge clk) begin
798
      if (USE_WAIT_REQUEST == 0) begin
799
         if (reset) begin
800
            local_avs_waitrequest = 0;
801
            read_wait_time = 0;
802
            write_wait_time = 0;
803
         end else begin
804
            local_avs_waitrequest = 0;
805
            if (AV_READ_WAIT_TIME > 0) begin
806
               #1;
807
               if (avs_read) begin
808
                  if (read_wait_time < AV_READ_WAIT_TIME) begin
809
                     local_avs_waitrequest = 1;
810
                     read_wait_time++;
811
                  end else begin
812
                     local_avs_waitrequest = 0;
813
                     read_wait_time = 0;
814
                  end
815
               end
816
            end
817
 
818
            if (AV_WRITE_WAIT_TIME > 0) begin
819
               #1;
820
               if (avs_write) begin
821
                  if (write_wait_time < AV_WRITE_WAIT_TIME) begin
822
                     local_avs_waitrequest = 1;
823
                     write_wait_time++;
824
                  end else begin
825
                     local_avs_waitrequest = 0;
826
                     write_wait_time = 0;
827
                  end
828
               end
829
            end
830
         end
831
      end else begin
832
         local_avs_waitrequest = avm_waitrequest;
833
      end
834
   end
835
 
836
   // synthesis translate_on
837
 
838
   function integer log2(
839
    input int value
840
    );
841
//-----------------------------------------------------------------------------
842
// Mathematic logarithm function with base as 2.
843
//-----------------------------------------------------------------------------
844
      value = value-1;
845
      for (log2=0; value>0; log2=log2+1)
846
      begin
847
         value = value>>1;
848
      end
849
 
850
   endfunction: log2
851
 
852
   function logic [lindex(AV_ADDRESS_W):0] address_shift(
853
    input logic [lindex(AV_ADDRESS_W):0] value
854
    );
855
//-----------------------------------------------------------------------------
856
// Shift the slave interface address back as master interface address.
857
//-----------------------------------------------------------------------------
858
      if (value >= 0)
859
         address_shift = value << log2(AV_NUMSYMBOLS);
860
      else
861
         address_shift = 'x;
862
 
863
   endfunction: address_shift
864
 
865
endmodule
866
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.