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// (C) 2001-2016 Intel Corporation. All rights reserved.
2
// Your use of Intel Corporation's design tools, logic functions and other
3
// software and tools, and its AMPP partner logic functions, and any output
4
// files any of the foregoing (including device programming or simulation
5
// files), and any associated documentation or information are expressly subject
6
// to the terms and conditions of the Intel Program License Subscription
7
// Agreement, Intel MegaCore Function License Agreement, or other applicable
8
// license agreement, including, without limitation, that your use is for the
9
// sole purpose of programming logic devices manufactured by Intel and sold by
10
// Intel or its authorized distributors.  Please refer to the applicable
11
// agreement for further details.
12
 
13
 
14
// $File: //acds/rel/16.1/ip/sopc/components/verification/altera_avalon_mm_monitor_bfm/altera_avalon_mm_monitor_assertion.sv $
15
// $Revision: #1 $
16
// $Date: 2016/08/07 $
17
//-----------------------------------------------------------------------------
18
// =head1 NAME
19
// altera_avalon_mm_monitor_assertion
20
// =head1 SYNOPSIS
21
// Memory Mapped Avalon Bus Protocol Checker
22
//-----------------------------------------------------------------------------
23
// =head1 DESCRIPTION
24
// This module implements Avalon MM protocol assertion checking for simulation.
25
//-----------------------------------------------------------------------------
26
 
27
`timescale 1ps / 1ps
28
 
29
module altera_avalon_mm_monitor_assertion(
30
                                          clk,
31
                                          reset,
32
                                          tap
33
                                         );
34
 
35
   // =head1 PARAMETERS
36
   parameter AV_ADDRESS_W               = 32;   // address width
37
   parameter AV_SYMBOL_W                = 8;    // default symbol is byte
38
   parameter AV_NUMSYMBOLS              = 4;    // number of symbols per word
39
   parameter AV_BURSTCOUNT_W            = 3;    // burst port width
40
 
41
   parameter AV_CONSTANT_BURST_BEHAVIOR = 1;    // Address, burstcount and
42
                                                // avm_writeresponserequest need to be held constant
43
                                                // in burst transaction
44
   parameter AV_BURST_LINEWRAP          = 0;    // line wrapping addr is set to 1
45
   parameter AV_BURST_BNDR_ONLY         = 0;    // addr is multiple of burst size
46
   parameter REGISTER_WAITREQUEST       = 0;    // Waitrequest is registered at the slave
47
   parameter AV_MAX_PENDING_READS       = 1;    // maximum pending read transfer count
48
   parameter AV_MAX_PENDING_WRITES      = 0;    // maximum pending write transfer count
49
   parameter AV_FIX_READ_LATENCY        = 0;    // fixed read latency in cycles
50
 
51
   parameter USE_READ                   = 1;    // use read port
52
   parameter USE_WRITE                  = 1;    // use write port
53
   parameter USE_ADDRESS                = 1;    // use address port
54
   parameter USE_BYTE_ENABLE            = 1;    // use byteenable port
55
   parameter USE_BURSTCOUNT             = 0;    // use burstcount port
56
   parameter USE_READ_DATA              = 1;    // use readdata port
57
   parameter USE_READ_DATA_VALID        = 1;    // use readdatavalid port
58
   parameter USE_WRITE_DATA             = 1;    // use writedata port
59
   parameter USE_BEGIN_TRANSFER         = 0;    // use begintransfer port
60
   parameter USE_BEGIN_BURST_TRANSFER   = 0;    // use begintbursttransfer port
61
   parameter USE_WAIT_REQUEST           = 1;    // use waitrequest port
62
   parameter USE_ARBITERLOCK            = 0;    // Use arbiterlock pin on interface
63
   parameter USE_LOCK                   = 0;    // Use lock pin on interface
64
   parameter USE_DEBUGACCESS            = 0;    // Use debugaccess pin on interface
65
   parameter USE_TRANSACTIONID          = 0;    // Use transactionid interface pin
66
   parameter USE_WRITERESPONSE          = 0;    // Use write response interface pins
67
   parameter USE_READRESPONSE           = 0;    // Use read response interface pins
68
   parameter USE_CLKEN                  = 0;    // Use clken interface pins
69
 
70
   parameter AV_READ_TIMEOUT            = 100;  // timeout period for read transfer
71
   parameter AV_WRITE_TIMEOUT           = 100;  // timeout period for write burst transfer
72
   parameter AV_WAITREQUEST_TIMEOUT     = 1024; // timeout period for continuous waitrequest
73
   parameter AV_MAX_READ_LATENCY        = 100;  // maximum read latency cycle for coverage
74
   parameter AV_MAX_WAITREQUESTED_READ  = 100;  // maximum waitrequested read cycle for coverage
75
   parameter AV_MAX_WAITREQUESTED_WRITE = 100;  // maximum waitrequested write cycle for coverage
76
   parameter string SLAVE_ADDRESS_TYPE = "SYMBOLS";   // Set slave interface address type, {SYMBOLS, WORDS}
77
   parameter string MASTER_ADDRESS_TYPE = "SYMBOLS";  // Set master interface address type, {SYMBOLS, WORDS}
78
 
79
   parameter AV_READ_WAIT_TIME         = 0;     // Fixed wait time cycles when
80
   parameter AV_WRITE_WAIT_TIME        = 0;     // USE_WAIT_REQUEST is 0
81
 
82
   parameter AV_REGISTERINCOMINGSIGNALS = 0;    // Indicate that waitrequest is come from register
83
 
84
   localparam AV_DATA_W = AV_SYMBOL_W * AV_NUMSYMBOLS;
85
   localparam AV_MAX_BURST = USE_BURSTCOUNT ? 2**(lindex(AV_BURSTCOUNT_W)) : 1;
86
   localparam INT_WIDTH = 32;
87
   localparam MAX_ID = (AV_MAX_PENDING_READS*AV_MAX_BURST > 100? AV_MAX_PENDING_READS*AV_MAX_BURST:100);
88
   localparam AV_TRANSACTIONID_W = 8;
89
 
90
   localparam TAP_W = 1 +                                                  // clken
91
                      1 +                                                  // arbiterlock
92
                      1 +                                                  // lock
93
                      1 +                                                  // debugaccess
94
                      ((AV_TRANSACTIONID_W == 0)? 1:AV_TRANSACTIONID_W) +  // transactionid
95
                      ((AV_TRANSACTIONID_W == 0)? 1:AV_TRANSACTIONID_W) +  // readid
96
                      ((AV_TRANSACTIONID_W == 0)? 1:AV_TRANSACTIONID_W) +  // avm_writeid
97
                      2 +                                                  // response
98
                      1 +                                                  // writeresponserequest
99
                      1 +                                                  // writeresponsevalid
100
                      1 +                                                  // waitrequest
101
                      1 +                                                  // readdatavalid
102
                      ((AV_DATA_W == 0)? 1:AV_DATA_W) +                    // readdata
103
                      1 +                                                  // write
104
                      1 +                                                  // read
105
                      ((AV_ADDRESS_W == 0)? 1:AV_ADDRESS_W) +              // address
106
                      ((AV_NUMSYMBOLS == 0)? 1:AV_NUMSYMBOLS) +            // byteenable
107
                      ((AV_BURSTCOUNT_W == 0)? 1:AV_BURSTCOUNT_W) +        // burstcount
108
                      1 +                                                  // beginbursttransfer
109
                      1 +                                                  // begintransfer
110
                      ((AV_DATA_W == 0)? 1:AV_DATA_W);                     // writedata
111
 
112
   // =head1 PINS
113
   // =head2 Clock Interface
114
   input                                             clk;
115
   input                                             reset;
116
 
117
   // =head2 Avalon Monitor Interface
118
   // Interface consists of Avalon Memory-Mapped Interface.
119
   // =cut
120
 
121
   // =pod
122
   input  [TAP_W-1:0]                                tap;
123
   // =cut
124
 
125
   function int lindex;
126
      // returns the left index for a vector having a declared width
127
      // when width is 0, then the left index is set to 0 rather than -1
128
      input [31:0] width;
129
      lindex = (width > 0) ? (width-1) : 0;
130
   endfunction
131
 
132
   //--------------------------------------------------------------------------
133
   // synthesis translate_off
134
 
135
   import verbosity_pkg::*;
136
   import avalon_mm_pkg::*;
137
 
138
   typedef bit [lindex(AV_ADDRESS_W):0]                    AvalonAddress_t;
139
   typedef bit [lindex(AV_BURSTCOUNT_W):0]                 AvalonBurstCount_t;
140
   typedef bit [AV_MAX_BURST-1:0][AV_DATA_W-1:0]     AvalonData_t;
141
   typedef bit [AV_MAX_BURST-1:0][AV_NUMSYMBOLS-1:0] AvalonByteEnable_t;
142
   typedef bit [AV_MAX_BURST-1:0][INT_WIDTH-1:0]     AvalonLatency_t;
143
   typedef bit [AV_MAX_BURST-1:0][1:0]               AvalonReadResponseStatus_t;
144
 
145
   typedef struct packed {
146
                          Request_t                  request;
147
                          AvalonAddress_t            address;     // start address
148
                          AvalonBurstCount_t         burst_count; // burst length
149
                          AvalonData_t               data;        // write data
150
                          AvalonByteEnable_t         byte_enable; // hot encoded
151
                          int                        burst_cycle;
152
                          logic                      write_response_request;
153
                         } SlaveCommand_t;
154
 
155
   typedef struct packed {
156
                          Request_t                  request;
157
                          AvalonAddress_t            address;     // start addr
158
                          AvalonBurstCount_t         burst_count; // burst length
159
                          AvalonData_t               data;        // read data
160
                          AvalonLatency_t            read_latency;
161
                          AvalonLatency_t            wait_latency;
162
                          AvalonReadResponseStatus_t read_response;
163
                          AvalonResponseStatus_t     write_response;
164
                         } MasterResponse_t;
165
 
166
   event                                  event_a_half_cycle_reset_legal;
167
   event                                  event_a_no_read_during_reset;
168
   event                                  event_a_no_write_during_reset;
169
   event                                  event_a_exclusive_read_write;
170
   event                                  event_a_begintransfer_single_cycle;
171
   event                                  event_a_begintransfer_legal;
172
   event                                  event_a_begintransfer_exist;
173
   event                                  event_a_beginbursttransfer_single_cycle;
174
   event                                  event_a_beginbursttransfer_legal;
175
   event                                  event_a_beginbursttransfer_exist;
176
   event                                  event_a_less_than_burstcount_max_size;
177
   event                                  event_a_byteenable_legal;
178
   event                                  event_a_constant_during_waitrequest;
179
   event                                  event_a_constant_during_burst;
180
   event                                  event_a_burst_legal;
181
   event                                  event_a_waitrequest_during_reset;
182
   event                                  event_a_no_readdatavalid_during_reset;
183
   event                                  event_a_less_than_maximumpendingreadtransactions;
184
   event                                  event_a_waitrequest_timeout;
185
   event                                  event_a_write_burst_timeout;
186
   event                                  event_a_read_response_timeout;
187
   event                                  event_a_read_response_sequence;
188
   event                                  event_a_readid_sequence;
189
   event                                  event_a_writeid_sequence;
190
   event                                  event_a_constant_during_clk_disabled;
191
   event                                  event_a_register_incoming_signals;
192
   event                                  event_a_address_align_with_data_width;
193
   event                                  event_a_write_response_timeout;
194
   event                                  event_a_unrequested_write_response;
195
 
196
 
197
   bit [1:0]                              reset_flag = 2'b11;
198
   bit                                    read_transaction_flag = 0;
199
   bit                                    read_without_waitrequest_flag = 0;
200
   bit                                    byteenable_legal_flag = 0;
201
   bit                                    byteenable_single_bit_flag = 0;
202
   bit                                    byteenable_continual_bit_flag = 0;
203
   bit                                    reset_half_cycle_flag = 0;
204
   logic [MAX_ID:0]                       read_response_timeout_start_flag = 0;
205
 
206
   bit                                    enable_a_half_cycle_reset_legal = 1;
207
   bit                                    enable_a_no_read_during_reset = 1;
208
   bit                                    enable_a_no_write_during_reset = 1;
209
   bit                                    enable_a_exclusive_read_write = 1;
210
   bit                                    enable_a_begintransfer_single_cycle = 1;
211
   bit                                    enable_a_begintransfer_legal = 1;
212
   bit                                    enable_a_begintransfer_exist = 1;
213
   bit                                    enable_a_beginbursttransfer_single_cycle = 1;
214
   bit                                    enable_a_beginbursttransfer_legal = 1;
215
   bit                                    enable_a_beginbursttransfer_exist = 1;
216
   bit                                    enable_a_less_than_burstcount_max_size = 1;
217
   bit                                    enable_a_byteenable_legal = 1;
218
   bit                                    enable_a_constant_during_waitrequest = 1;
219
   bit                                    enable_a_constant_during_burst = 1;
220
   bit                                    enable_a_burst_legal = 1;
221
   bit                                    enable_a_waitrequest_during_reset = 1;
222
   bit                                    enable_a_no_readdatavalid_during_reset = 1;
223
   bit                                    enable_a_less_than_maximumpendingreadtransactions = 1;
224
   bit                                    enable_a_waitrequest_timeout = 1;
225
   bit                                    enable_a_write_burst_timeout = 1;
226
   bit                                    enable_a_read_response_timeout = 1;
227
   bit                                    enable_a_read_response_sequence = 1;
228
   bit                                    enable_a_readid_sequence = 0;
229
   bit                                    enable_a_writeid_sequence = 0;
230
   bit                                    enable_a_constant_during_clk_disabled = 1;
231
   bit                                    enable_a_register_incoming_signals = 1;
232
   bit                                    enable_a_address_align_with_data_width = 1;
233
   bit                                    enable_a_write_response_timeout = 1;
234
   bit                                    enable_a_unrequested_write_response = 1;
235
 
236
   int                                    write_burst_counter = 0;
237
   int                                    pending_read_counter = 0;
238
   int                                    write_burst_timeout_counter = 0;
239
   int                                    waitrequest_timeout_counter = 0;
240
   logic [MAX_ID:0][31:0]                 temp_read_response_timeout_counter = 0;
241
   int                                    read_response_timeout_counter = 0;
242
   int                                    read_id = 0;
243
   int                                    readdatavalid_id = 0;
244
   int                                    byteenable_bit_counter = 0;
245
   int                                    reset_counter = 1;
246
   bit                                    write_burst_completed = 0;
247
   logic [MAX_ID:0][lindex(AV_BURSTCOUNT_W):0] read_burst_counter = 0;
248
   logic [AV_TRANSACTIONID_W-1:0]         write_transactionid_queued[$];
249
   logic [AV_TRANSACTIONID_W-1:0]         read_transactionid_queued[$];
250
   int                                    write_response_burstcount = 0;
251
   int                                    write_burstcount_queued[$];
252
   int                                    read_response_burstcount = 0;
253
   int                                    read_burstcount_queued[$];
254
   int                                    temp_write_transactionid_queued = 0;
255
   int                                    temp_read_transactionid_queued = 0;
256
   int                                    fix_latency_queued[$];
257
   int                                    fix_latency_queued_counter = 0;
258
   int                                    pending_write_response = 0;
259
   int                                    write_response_timeout = 100;
260
   logic [lindex(AV_MAX_PENDING_WRITES):0][31:0] write_response_timeout_counter;
261
   logic                                  past_readdatavalid = 0;
262
   logic                                  past_writeresponsevalid = 0;
263
   logic [lindex(AV_TRANSACTIONID_W):0]   past_writeid;
264
   logic [lindex(AV_TRANSACTIONID_W):0]   past_readid;
265
   logic                                  round_over = 0;
266
   logic                                  command_while_clken = 0;
267
   logic                                  waitrequested_command_while_clken = 0;
268
 
269
   //--------------------------------------------------------------------------
270
   // unpack Avalon bus interface tap into individual port signals
271
 
272
   logic                                  waitrequest;
273
   logic                                  readdatavalid;
274
   logic [lindex(AV_DATA_W):0]            readdata;
275
   logic                                  write;
276
   logic                                  read;
277
   logic [lindex(AV_ADDRESS_W):0]         address;
278
   logic [lindex(AV_NUMSYMBOLS):0]        byteenable;
279
   logic [lindex(AV_BURSTCOUNT_W):0]      burstcount;
280
   logic                                  beginbursttransfer;
281
   logic                                  begintransfer;
282
   logic [lindex(AV_DATA_W):0]            writedata;
283
   logic                                  arbiterlock;
284
   logic                                  lock;
285
   logic                                  debugaccess;
286
 
287
   logic [lindex(AV_TRANSACTIONID_W):0]   transactionid;
288
   logic [lindex(AV_TRANSACTIONID_W):0]   readid;
289
   logic [lindex(AV_TRANSACTIONID_W):0]   writeid;
290
   logic [1:0]                            response;
291
   logic                                  writeresponserequest;
292
   logic                                  writeresponsevalid;
293
   logic                                  clken;
294
 
295
   always_comb begin
296
 
297
      clken <= (USE_CLKEN == 1)?
298
                      tap[3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+21:
299
                          3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+21] : 1;
300
 
301
      arbiterlock <= (USE_ARBITERLOCK == 1)?
302
                      tap[3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+20:
303
                          3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+20] : 0;
304
 
305
      lock <= (USE_LOCK == 1)?
306
                      tap[3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+19:
307
                          3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+19] : 0;
308
 
309
      debugaccess <= (USE_DEBUGACCESS == 1)?
310
                      tap[3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+18:
311
                          3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+18] : 0;
312
 
313
      transactionid <= (USE_TRANSACTIONID == 1)?
314
                      tap[3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+17:
315
                          2*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+17] : 0;
316
 
317
      readid <= (USE_READRESPONSE == 1)?
318
                      tap[2*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+16:
319
                          lindex(AV_TRANSACTIONID_W)+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+16] : 0;
320
 
321
      writeid <= (USE_WRITERESPONSE == 1)?
322
                      tap[lindex(AV_TRANSACTIONID_W)+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+15:
323
                          2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+15] : 0;
324
 
325
      response <= (USE_WRITERESPONSE == 1 || USE_READRESPONSE == 1)?
326
                 tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+14:
327
                     2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+13] : 0;
328
 
329
      writeresponserequest <= (USE_WRITERESPONSE == 1)?
330
                      tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+12:
331
                          2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+12] : 0;
332
 
333
      writeresponsevalid <= (USE_WRITERESPONSE == 1)?
334
                      tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+11:
335
                          2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+11] : 0;
336
 
337
      waitrequest <= tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+10:
338
                          2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+10];
339
 
340
      readdatavalid <= (USE_READ_DATA_VALID == 1)?
341
                        tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+9:
342
                            2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+9] : 0;
343
 
344
      readdata <= (USE_READ_DATA == 1)?
345
                   tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+8:
346
                       lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+8] : 0;
347
 
348
      write <= (USE_WRITE == 1)?
349
                tap[lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+7:
350
                    lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+7] : 0;
351
 
352
      read <= (USE_READ == 1)?
353
               tap[lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+6:
354
                   lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+6] : 0;
355
 
356
      address <= (USE_ADDRESS == 1)?
357
                  tap[lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+5:
358
                      lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+5] : 0;
359
 
360
      byteenable <= (USE_BYTE_ENABLE == 1)?
361
                     tap[lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+4:
362
                         lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+4] : 0;
363
 
364
      burstcount <= (USE_BURSTCOUNT == 1)?
365
                     tap[lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+3: lindex(AV_DATA_W)+3] : 1;
366
 
367
      beginbursttransfer <= (USE_BEGIN_BURST_TRANSFER == 1)?
368
                             tap[lindex(AV_DATA_W)+2:lindex(AV_DATA_W)+2] : 0;
369
 
370
      begintransfer <= (USE_BEGIN_TRANSFER == 1)? tap[lindex(AV_DATA_W)+1:lindex(AV_DATA_W)+1] : 0;
371
 
372
      writedata <= (USE_WRITE_DATA == 1)? tap[lindex(AV_DATA_W):0] : 0;
373
   end
374
 
375
   //--------------------------------------------------------------------------
376
   // =head1 Public Methods API
377
   // This section describes the public methods in the application programming
378
   // interface (API). In this case the application program is the test bench
379
   // which instantiates and controls and queries state of this component.
380
   // Test programs must only use these public access methods and events to
381
   // communicate with this BFM component. The API and the module pins
382
   // are the only interfaces in this component that are guaranteed to be
383
   // stable. The API will be maintained for the life of the product.
384
   // While we cannot prevent a test program from directly accessing internal
385
   // tasks, functions, or data private to the BFM, there is no guarantee that
386
   // these will be present in the future. In fact, it is best for the user
387
   // to assume that the underlying implementation of this component can
388
   // and will change.
389
   // =cut
390
   //--------------------------------------------------------------------------
391
 
392
   // Master Assertions API
393
   function automatic void set_enable_a_half_cycle_reset_legal( // public
394
      bit     assert_enable
395
   );
396
   // enable or disable a_half_cycle_reset_legal assertion
397
 
398
      enable_a_half_cycle_reset_legal = assert_enable;
399
   endfunction
400
 
401
   function automatic void set_enable_a_no_read_during_reset( // public
402
      bit     assert_enable
403
   );
404
   // enable or disable a_no_read_during_reset assertion
405
 
406
      enable_a_no_read_during_reset = assert_enable;
407
   endfunction
408
 
409
   function automatic void set_enable_a_no_write_during_reset( // public
410
      bit     assert_enable
411
   );
412
   // enable or disable a_no_write_during_reset assertion
413
 
414
      enable_a_no_write_during_reset = assert_enable;
415
   endfunction
416
 
417
   function automatic void set_enable_a_exclusive_read_write( // public
418
      bit     assert_enable
419
   );
420
   // enable or disable a_exclusive_read_write assertion
421
 
422
      enable_a_exclusive_read_write = assert_enable;
423
   endfunction
424
 
425
   function automatic void set_enable_a_begintransfer_single_cycle( // public
426
      bit     assert_enable
427
   );
428
   // enable or disable a_begintransfer_single_cycle assertion
429
 
430
      enable_a_begintransfer_single_cycle = assert_enable;
431
   endfunction
432
 
433
   function automatic void set_enable_a_begintransfer_legal( // public
434
      bit     assert_enable
435
   );
436
   // enable or disable a_begintransfer_legal assertion
437
 
438
      enable_a_begintransfer_legal = assert_enable;
439
   endfunction
440
 
441
   function automatic void set_enable_a_begintransfer_exist( // public
442
      bit     assert_enable
443
   );
444
   // enable or disable a_begintransfer_exist assertion
445
 
446
      enable_a_begintransfer_exist = assert_enable;
447
   endfunction
448
 
449
   function automatic void set_enable_a_beginbursttransfer_single_cycle( // public
450
      bit     assert_enable
451
   );
452
   // enable or disable a_beginbursttransfer_single_cycle assertion
453
 
454
      enable_a_beginbursttransfer_single_cycle = assert_enable;
455
   endfunction
456
 
457
   function automatic void set_enable_a_beginbursttransfer_legal( // public
458
      bit     assert_enable
459
   );
460
   // enable or disable a_beginbursttransfer_legal assertion
461
 
462
      enable_a_beginbursttransfer_legal = assert_enable;
463
   endfunction
464
 
465
   function automatic void set_enable_a_beginbursttransfer_exist( // public
466
      bit     assert_enable
467
   );
468
   // enable or disable a_beginbursttransfer_exist assertion
469
 
470
      enable_a_beginbursttransfer_exist = assert_enable;
471
   endfunction
472
 
473
   function automatic void set_enable_a_less_than_burstcount_max_size( // public
474
      bit     assert_enable
475
   );
476
   // enable or disable a_less_than_burstcount_max_size assertion
477
 
478
      enable_a_less_than_burstcount_max_size = assert_enable;
479
   endfunction
480
 
481
   function automatic void set_enable_a_byteenable_legal( // public
482
      bit     assert_enable
483
   );
484
   // enable or disable a_byteenable_legal assertion
485
 
486
      enable_a_byteenable_legal = assert_enable;
487
   endfunction
488
 
489
   function automatic void set_enable_a_constant_during_waitrequest( // public
490
      bit     assert_enable
491
   );
492
   // enable or disable a_constant_during_waitrequest assertion
493
 
494
      enable_a_constant_during_waitrequest = assert_enable;
495
   endfunction
496
 
497
   function automatic void set_enable_a_constant_during_burst( // public
498
      bit     assert_enable
499
   );
500
   // enable or disable a_constant_during_burst assertion
501
 
502
      enable_a_constant_during_burst = assert_enable;
503
   endfunction
504
 
505
   function automatic void set_enable_a_burst_legal( // public
506
      bit     assert_enable
507
   );
508
   // enable or disable a_burst_legal assertion
509
 
510
      enable_a_burst_legal = assert_enable;
511
   endfunction
512
 
513
   // Slave Assertions API
514
   function automatic void set_enable_a_waitrequest_during_reset( // public
515
      bit     assert_enable
516
   );
517
   // enable or disable a_waitrequest_during_reset assertion
518
 
519
      enable_a_waitrequest_during_reset = assert_enable;
520
   endfunction
521
 
522
   function automatic void set_enable_a_no_readdatavalid_during_reset( // public
523
      bit     assert_enable
524
   );
525
   // enable or disable a_no_readdatavalid_during_reset assertion
526
 
527
      enable_a_no_readdatavalid_during_reset = assert_enable;
528
   endfunction
529
 
530
   function automatic void set_enable_a_less_than_maximumpendingreadtransactions( // public
531
      bit     assert_enable
532
   );
533
   // enable or disable a_less_than_maximumpendingreadtransactions assertion
534
 
535
      enable_a_less_than_maximumpendingreadtransactions = assert_enable;
536
   endfunction
537
 
538
   function automatic void set_enable_a_read_response_sequence( // public
539
      bit     assert_enable
540
   );
541
   // enable or disable a_read_response_sequence assertion
542
 
543
      enable_a_read_response_sequence = assert_enable;
544
   endfunction
545
 
546
   function automatic void set_enable_a_readid_sequence( // public
547
      bit     assert_enable
548
   );
549
   // enable or disable a_readid_sequence assertion
550
 
551
      enable_a_readid_sequence = assert_enable;
552
   endfunction
553
 
554
   function automatic void set_enable_a_writeid_sequence( // public
555
      bit     assert_enable
556
   );
557
   // enable or disable a_writeid_sequence assertion
558
 
559
      enable_a_writeid_sequence = assert_enable;
560
   endfunction
561
   // Timeout Assertions API
562
   function automatic void set_enable_a_waitrequest_timeout( // public
563
      bit     assert_enable
564
   );
565
   // enable or disable a_waitrequest_timeout assertion
566
 
567
      enable_a_waitrequest_timeout = assert_enable;
568
   endfunction
569
 
570
   function automatic void set_enable_a_write_burst_timeout( // public
571
      bit     assert_enable
572
   );
573
   // enable or disable a_write_burst_timeout assertion
574
 
575
      enable_a_write_burst_timeout = assert_enable;
576
   endfunction
577
 
578
   function automatic void set_enable_a_read_response_timeout( // public
579
      bit     assert_enable
580
   );
581
   // enable or disable a_read_response_timeout assertion
582
 
583
      enable_a_read_response_timeout = assert_enable;
584
   endfunction
585
 
586
   function automatic void set_enable_a_constant_during_clk_disabled( // public
587
      bit     assert_enable
588
   );
589
   // enable or disable a_constant_during_clk_disabled assertion
590
 
591
      enable_a_constant_during_clk_disabled = assert_enable;
592
   endfunction
593
 
594
   function automatic void set_enable_a_register_incoming_signals( // public
595
      bit     assert_enable
596
   );
597
   // enable or disable a_register_incoming_signals assertion
598
 
599
      enable_a_register_incoming_signals = assert_enable;
600
   endfunction
601
 
602
   function automatic void set_enable_a_address_align_with_data_width( // public
603
      bit     assert_enable
604
   );
605
   // enable or disable a_address_align_with_data_width assertion
606
 
607
      enable_a_address_align_with_data_width = assert_enable;
608
   endfunction
609
 
610
   function automatic void set_enable_a_write_response_timeout( // public
611
      bit     assert_enable
612
   );
613
   // enable or disable a_write_response_timeout assertion
614
 
615
      enable_a_write_response_timeout = assert_enable;
616
   endfunction
617
 
618
   function automatic void set_enable_a_unrequested_write_response( // public
619
      bit     assert_enable
620
   );
621
   // enable or disable a_unrequested_write_response assertion
622
 
623
      enable_a_unrequested_write_response = assert_enable;
624
   endfunction
625
 
626
   function automatic void set_write_response_timeout( // public
627
      int     cycles = 100
628
   );
629
   // set timeout for write response
630
 
631
      write_response_timeout = cycles;
632
   endfunction
633
 
634
   //--------------------------------------------------------------------------
635
   // =head1 Assertion Checkers and Coverage Monitors
636
   // The assertion checkers in this module are only executable on simulators
637
   // supporting the SystemVerilog Assertion (SVA) language.
638
   // Mentor Modelsim AE and SE do not support this.
639
   // Simulators that are supported include: Synopsys VCS and Mentor questasim.
640
   // The assertion checking logic in this module must be explicitly enabled
641
   // so that designs using this module can still be compiled on Modelsim without
642
   // changes. To disable assertions define the following macro in the testbench
643
   // or on the command line with: +define+DISABLE_ALTERA_AVALON_SIM_SVA.
644
   // =cut
645
   //--------------------------------------------------------------------------
646
 
647
   string   str_assertion;
648
 
649
   function automatic void print_assertion(
650
      string message_in
651
   );
652
      string message_out;
653
      $sformat(message_out, "ASSERTION: %m: %s", message_in);
654
      print(VERBOSITY_FAILURE, message_out);
655
   endfunction
656
 
657
   // previous cycle value of signals
658
   always @(posedge clk) begin
659
      past_readdatavalid = readdatavalid;
660
      past_writeresponsevalid = writeresponsevalid;
661
      past_readid = readid;
662
      past_writeid = writeid;
663
   end
664
 
665
   // Counter for general assertion counters
666
   always @(posedge clk) begin
667
 
668
      if (!USE_CLKEN || clken) begin
669
         // ignore the waitrequest effect while reset
670
         if ((read || write) &&
671
         reset_flag[1] == 0)
672
            reset_flag[0] = 0;
673
         if (($fell(read) || $fell(write) || readdatavalid ||
674
         $fell(begintransfer) || $fell(beginbursttransfer) ||
675
         ((read || write) && $fell(waitrequest))) &&
676
         reset_flag[0] == 0) begin
677
            reset_flag[1] = 1;
678
            reset_flag[0] = 1;
679
         end
680
 
681
         // counter for readdatavalid_id and read response timeout check
682
         if ((!read || (read && waitrequest)) && !readdatavalid) begin
683
            read_response_timeout_counter = 0;
684
         end
685
         if (read && !waitrequest && !readdatavalid) begin
686
            if (((!$fell(waitrequest) && !waitrequested_command_while_clken) ||
687
            $rose(read)) || command_while_clken || reset_flag[1] == 0) begin
688
               read_response_timeout_start_flag[read_id] = 1;
689
               temp_read_response_timeout_counter[read_id] = 0;
690
            end else begin
691
               if (read_id != 0) begin
692
                  read_response_timeout_start_flag[read_id-1] = 1;
693
                  temp_read_response_timeout_counter[read_id-1] = 0;
694
                end else begin
695
                  read_response_timeout_start_flag[MAX_ID] = 1;
696
                  temp_read_response_timeout_counter[MAX_ID] = 0;
697
                end
698
            end
699
         end
700
 
701
         if (!read && readdatavalid) begin
702
            read_response_timeout_counter =
703
               temp_read_response_timeout_counter[readdatavalid_id]-1;
704
            if (read_burst_counter[readdatavalid_id] == 1 ||
705
            read_burst_counter[readdatavalid_id] == 0) begin
706
               temp_read_response_timeout_counter[readdatavalid_id] = 0;
707
               read_response_timeout_start_flag[readdatavalid_id] = 0;
708
               if (readdatavalid_id < (MAX_ID))
709
                  readdatavalid_id++;
710
               else
711
                  readdatavalid_id = 0;
712
            end
713
         end
714
         if (read && readdatavalid) begin
715
            read_response_timeout_counter =
716
               temp_read_response_timeout_counter[readdatavalid_id]-1;
717
            if (!waitrequest) begin
718
               if (((!$fell(waitrequest) && !waitrequested_command_while_clken) ||
719
               $rose(read)) || command_while_clken || reset_flag[1] == 0) begin
720
                  read_response_timeout_start_flag[read_id] = 1;
721
                  temp_read_response_timeout_counter[read_id] = 0;
722
               end else begin
723
                  if (read_id != 0) begin
724
                     read_response_timeout_start_flag[read_id-1] = 1;
725
                     temp_read_response_timeout_counter[read_id-1] = 0;
726
                  end else begin
727
                     read_response_timeout_start_flag[MAX_ID] = 1;
728
                     temp_read_response_timeout_counter[MAX_ID] = 0;
729
                  end
730
               end
731
            end
732
            if (read_burst_counter[readdatavalid_id] == 1 ||
733
            read_burst_counter[readdatavalid_id] == 0) begin
734
               temp_read_response_timeout_counter[readdatavalid_id] = 0;
735
               read_response_timeout_start_flag[readdatavalid_id] = 0;
736
               if (readdatavalid_id < (MAX_ID))
737
                  readdatavalid_id++;
738
               else
739
                  readdatavalid_id = 0;
740
            end
741
         end
742
 
743
         // new burst write transaction started
744
         if (($rose(write) || (write && ((!waitrequest && ((!$fell(waitrequest) &&
745
         !waitrequested_command_while_clken) || reset_flag[1] == 0)) ||
746
         command_while_clken || ($rose(waitrequest))))) &&
747
         write_burst_counter == 0 && burstcount > 0) begin
748
            write_burst_counter = burstcount;
749
            write_transactionid_queued.push_front(transactionid);
750
            temp_write_transactionid_queued = write_transactionid_queued[$];
751
            write_burstcount_queued.push_front(burstcount);
752
         end
753
 
754
         if (write && !waitrequest && write_burst_counter > 0)
755
            write_burst_counter--;
756
 
757
         // new read transaction asserted
758
         if (($rose(read) || (read && ((!waitrequest &&
759
         ((!$fell(waitrequest) && !waitrequested_command_while_clken) ||
760
         reset_flag[1] == 0)) || command_while_clken ||
761
         ($rose(waitrequest))))) || (read_transaction_flag && waitrequest &&
762
         read_without_waitrequest_flag && read)) begin
763
            read_transaction_flag = 1;
764
            read_transactionid_queued.push_front(transactionid);
765
            temp_read_transactionid_queued = read_transactionid_queued[$];
766
            read_burstcount_queued.push_front(burstcount);
767
         end else
768
            read_transaction_flag = 0;
769
 
770
         // new read transaction without previous read response(readdatavalid) returned at same cycle
771
         if ((($rose(read) || (read && ((!waitrequest &&
772
         ((!$fell(waitrequest) && !waitrequested_command_while_clken) ||
773
         reset_flag[1] == 0)) || command_while_clken ||
774
         ($rose(waitrequest))))) || (read_transaction_flag && waitrequest &&
775
         read_without_waitrequest_flag && read)) &&
776
         !readdatavalid) begin
777
            if (burstcount > 0)
778
               read_burst_counter[read_id] = burstcount;
779
            if (!waitrequest)
780
               read_without_waitrequest_flag = 1;
781
            else
782
               read_without_waitrequest_flag = 0;
783
            pending_read_counter++;
784
            if (read_id < (MAX_ID))
785
               read_id++;
786
            else
787
               read_id = 0;
788
         end
789
 
790
         // previous read response(readdatavalid) returned while no new read transaction asserted
791
         if ((readdatavalid ||
792
            (fix_latency_queued_counter != 0 &&
793
            fix_latency_queued_counter == AV_FIX_READ_LATENCY &&
794
            !USE_READ_DATA_VALID)) &&
795
            (!read_transaction_flag || !read) && pending_read_counter > 0) begin
796
            if ((readdatavalid_id == 0) && (read_burst_counter[MAX_ID] == 0)) begin
797
               round_over = 0;
798
               if (read_burst_counter[readdatavalid_id] > 0) begin
799
                  if (read_burst_counter[readdatavalid_id] == 1) begin
800
                     pending_read_counter--;
801
                  end
802
                  read_burst_counter[readdatavalid_id]--;
803
               end
804
            end else if (read_id >= ((readdatavalid_id == 0)?MAX_ID-1:readdatavalid_id-1)) begin
805
               round_over = 0;
806
               for (int i=0; i<=MAX_ID; i++) begin
807
                  if (read_burst_counter[i] > 0) begin
808
                     if (read_burst_counter[i] == 1) begin
809
                        pending_read_counter--;
810
                     end
811
                     read_burst_counter[i]--;
812
                     i=MAX_ID+1;
813
                  end
814
               end
815
            end else begin
816
               for (int i=((readdatavalid_id == 0)?MAX_ID-1:readdatavalid_id-1); i<=MAX_ID; i++) begin
817
                  round_over = 1;
818
                  if (read_burst_counter[i] > 0) begin
819
                     if (read_burst_counter[i] == 1) begin
820
                        pending_read_counter--;
821
                     end
822
                     read_burst_counter[i]--;
823
                     i=MAX_ID+1;
824
                  end
825
               end
826
            end
827
         end
828
 
829
         // new read transaction with previous read response(readdatavalid) returned at same cycle
830
         if ((($rose(read) || (read && ((!waitrequest &&
831
         ((!$fell(waitrequest) && !waitrequested_command_while_clken) ||
832
         reset_flag[1] == 0)) || command_while_clken ||
833
         ($rose(waitrequest))))) || (read_transaction_flag && waitrequest &&
834
         read_without_waitrequest_flag && read)) &&
835
         (readdatavalid || (fix_latency_queued_counter != 0 &&
836
         fix_latency_queued_counter == AV_FIX_READ_LATENCY &&
837
         !USE_READ_DATA_VALID))) begin
838
            if ((readdatavalid_id == 0) && (read_burst_counter[MAX_ID] == 0)) begin
839
               round_over = 0;
840
               if (read_burst_counter[readdatavalid_id] > 0) begin
841
                  if (read_burst_counter[readdatavalid_id] == 1) begin
842
                     pending_read_counter--;
843
                  end
844
                  read_burst_counter[readdatavalid_id]--;
845
               end
846
            end else if (read_id >= ((readdatavalid_id == 0)?MAX_ID-1:readdatavalid_id-1)) begin
847
               round_over = 0;
848
               for (int i=0; i<=MAX_ID; i++) begin
849
                  if (read_burst_counter[i] > 0) begin
850
                     if (read_burst_counter[i] == 1) begin
851
                        pending_read_counter--;
852
                     end
853
                     read_burst_counter[i]--;
854
                     i=MAX_ID+1;
855
                  end
856
               end
857
            end else begin
858
               for (int i=((readdatavalid_id == 0)?MAX_ID-1:readdatavalid_id-1); i<=MAX_ID; i++) begin
859
                  round_over = 1;
860
                  if (read_burst_counter[i] > 0) begin
861
                     if (read_burst_counter[i] == 1) begin
862
                        pending_read_counter--;
863
                     end
864
                     read_burst_counter[i]--;
865
                     i=MAX_ID+1;
866
                  end
867
               end
868
            end
869
 
870
            if (burstcount > 0)
871
               read_burst_counter[read_id] = burstcount;
872
            if (!waitrequest)
873
               read_without_waitrequest_flag = 1;
874
            else
875
               read_without_waitrequest_flag = 0;
876
            pending_read_counter++;
877
            if (read_id < (MAX_ID))
878
               read_id++;
879
            else
880
               read_id = 0;
881
         end
882
 
883
         // Counter for timeout
884
         if (pending_read_counter > 0) begin
885
            if (!USE_READ_DATA_VALID) begin
886
            end else begin
887
               for (int i=0; i<=MAX_ID; i++) begin
888
                  if (i != read_id) begin
889
                     if (read_response_timeout_start_flag[i])
890
                        temp_read_response_timeout_counter[i]++;
891
                  end
892
               end
893
            end
894
         end
895
 
896
         if (read || write_burst_counter == 0)
897
            write_burst_timeout_counter = 0;
898
         if (write_burst_counter != 0 || (write && beginbursttransfer))
899
            write_burst_timeout_counter++;
900
         if (waitrequest && (read || write))
901
            waitrequest_timeout_counter++;
902
         else
903
            waitrequest_timeout_counter = 0;
904
 
905
         // Counter for write response timeout checking
906
         if (pending_write_response > 0) begin
907
            for (int i = 0; i < pending_write_response; i++) begin
908
               write_response_timeout_counter[i]++;
909
            end
910
         end
911
 
912
         if (write == 1 && write_burst_counter == 0) begin
913
            write_response_timeout_counter[pending_write_response] = 0;
914
            pending_write_response++;
915
         end
916
 
917
         if (writeresponsevalid) begin
918
            if (pending_write_response > 0) begin
919
               pending_write_response--;
920
            end
921
            write_response_timeout_counter[0] = 0;
922
            for (int i = 0; i < pending_write_response; i++) begin
923
               write_response_timeout_counter[i] = write_response_timeout_counter[i+1];
924
            end
925
         end
926
 
927
         // Counter for writeresponse sequence checking
928
         if (writeresponsevalid) begin
929
            void'(write_transactionid_queued.pop_back());
930
            temp_write_transactionid_queued = write_transactionid_queued[$];
931
         end
932
 
933
         // Counter for readresponse sequence checking
934
         if (readdatavalid || ((fix_latency_queued_counter == AV_FIX_READ_LATENCY) &&
935
            (!USE_READ_DATA_VALID))) begin
936
            if (read_response_burstcount == 0) begin
937
               if (read_burstcount_queued.size() > 0)
938
                  read_response_burstcount = read_burstcount_queued.pop_back();
939
            end
940
            if (read_response_burstcount > 0)
941
               read_response_burstcount--;
942
            if (read_response_burstcount == 0) begin
943
               if (read_transactionid_queued.size() > 0)
944
                  void'(read_transactionid_queued.pop_back());
945
               temp_read_transactionid_queued = read_transactionid_queued[$];
946
            end
947
         end
948
 
949
         // fix latency counter
950
         if (read && !waitrequest) begin
951
            fix_latency_queued.push_front(0);
952
         end
953
 
954
         if (fix_latency_queued.size() > 0) begin
955
            foreach(fix_latency_queued[size]) begin
956
               fix_latency_queued[size]++;
957
               if (fix_latency_queued[size] > AV_FIX_READ_LATENCY) begin
958
                  void'(fix_latency_queued.pop_back());
959
               end
960
            end
961
            fix_latency_queued_counter = fix_latency_queued[$];
962
         end
963
         command_while_clken = 0;
964
         waitrequested_command_while_clken = 0;
965
      end else begin
966
         if (($rose(waitrequest) && (read || write)) ||
967
         ($rose(read) || $rose(write))) begin
968
            command_while_clken = 1;
969
         end
970
 
971
         if ($fell(waitrequest) && (read || write)) begin
972
               waitrequested_command_while_clken = 1;
973
            end
974
         end
975
   end
976
 
977
   // Counter for byteenable legality checking
978
   always @(posedge clk && byteenable >= 0) begin
979
      byteenable_bit_counter = 0;
980
      byteenable_legal_flag = 0;
981
      byteenable_single_bit_flag = 0;
982
      byteenable_continual_bit_flag = 0;
983
      for (int i=0; i
984
         if (byteenable[i]) begin
985
            if (!byteenable_single_bit_flag &&
986
                byteenable_bit_counter == 0) begin
987
               byteenable_single_bit_flag = 1;
988
               byteenable_continual_bit_flag = 0;
989
               byteenable_legal_flag = 0;
990
            end else if (byteenable_single_bit_flag &&
991
                         byteenable_bit_counter > 0) begin
992
               byteenable_single_bit_flag = 0;
993
               byteenable_continual_bit_flag = 1;
994
               byteenable_legal_flag = 0;
995
            end else if (!byteenable_single_bit_flag &&
996
                         !byteenable_continual_bit_flag &&
997
                         byteenable_bit_counter > 0) begin
998
               byteenable_legal_flag = 1;
999
               break;
1000
            end
1001
         byteenable_bit_counter++;
1002
         end else begin
1003
            if (byteenable_bit_counter > 0) begin
1004
               if (byteenable_single_bit_flag &&
1005
                   byteenable_bit_counter == 1) begin
1006
                  byteenable_single_bit_flag = 0;
1007
                  byteenable_continual_bit_flag = 0;
1008
                  byteenable_legal_flag = 0;
1009
               end else if (byteenable_continual_bit_flag &&
1010
                            byteenable_bit_counter > 1) begin
1011
                   if ((i != byteenable_bit_counter &&
1012
                       i%byteenable_bit_counter == 0) ||
1013
                       (i == byteenable_bit_counter &&
1014
                       AV_NUMSYMBOLS%i == 0)) begin
1015
                      byteenable_single_bit_flag = 0;
1016
                      byteenable_continual_bit_flag = 0;
1017
                      byteenable_legal_flag = 0;
1018
                   end else begin
1019
                      byteenable_legal_flag = 1;
1020
                      break;
1021
                   end
1022
                end
1023
             end else
1024
                byteenable_legal_flag = 0;
1025
          end
1026
      end
1027
      if (byteenable_bit_counter != 1 &&
1028
          byteenable_bit_counter != 2 &&
1029
          byteenable_bit_counter%4 != 0 &&
1030
          byteenable_legal_flag == 0) begin
1031
         byteenable_legal_flag = 1;
1032
      end
1033
   end
1034
 
1035
   // Counter for reset
1036
   always @(clk) begin
1037
      if (reset) begin
1038
         write_transactionid_queued = {};
1039
         read_transactionid_queued = {};
1040
         write_burstcount_queued = {};
1041
         read_burstcount_queued = {};
1042
         fix_latency_queued = {};
1043
         write_response_burstcount = 0;
1044
         read_response_burstcount = 0;
1045
         temp_write_transactionid_queued = 0;
1046
         temp_read_transactionid_queued = 0;
1047
         fix_latency_queued_counter = 0;
1048
         read_response_timeout_start_flag = 0;
1049
         temp_read_response_timeout_counter = 0;
1050
         read_burst_counter = 0;
1051
 
1052
         read_transaction_flag = 0;
1053
         read_without_waitrequest_flag = 0;
1054
         byteenable_legal_flag = 0;
1055
         byteenable_single_bit_flag = 0;
1056
         byteenable_continual_bit_flag = 0;
1057
         write_burst_counter = 0;
1058
         pending_read_counter = 0;
1059
         write_burst_timeout_counter = 0;
1060
         waitrequest_timeout_counter = 0;
1061
         read_response_timeout_counter = 0;
1062
         read_id = 0;
1063
         readdatavalid_id = 0;
1064
         byteenable_bit_counter = 0;
1065
         reset_counter++;
1066
         reset_flag[1] = 0;
1067
         reset_flag[0] = 1;
1068
         write_burst_completed = 0;
1069
         round_over = 0;
1070
         command_while_clken = 0;
1071
         waitrequested_command_while_clken = 0;
1072
         if ((reset_counter%2) == 1)
1073
            reset_half_cycle_flag = 1;
1074
         else
1075
            reset_half_cycle_flag = 0;
1076
      end
1077
      if (reset == 0) begin
1078
         reset_half_cycle_flag = 0;
1079
         reset_counter = 0;
1080
      end
1081
   end
1082
 
1083
   // SVA assertion code lives within the following section block
1084
   // which is disabled when the macro DISABLE_ALTERA_AVALON_SIM_SVA
1085
   // is defined
1086
 
1087
   `ifdef DISABLE_ALTERA_AVALON_SIM_SVA
1088
   // SVA assertion code has been disabled
1089
 
1090
   `else
1091
   //--------------------------------------------------------------------------
1092
   // ASSERTION CODE BEGIN
1093
   //--------------------------------------------------------------------------
1094
   //-------------------------------------------------------------------------------
1095
   // =head2 Master Assertions
1096
   // The following are the assertions code focus on Master component checking
1097
   //-------------------------------------------------------------------------------
1098
 
1099
   //-------------------------------------------------------------------------------
1100
   // =head3 a_half_cycle_reset_legal
1101
   // This property checks if reset is asserted correctly
1102
   //-------------------------------------------------------------------------------
1103
 
1104
   sequence s_reset_half_cycle;
1105
      reset_half_cycle_flag ##0
1106
         $rose(clk);
1107
   endsequence
1108
 
1109
   sequence s_reset_non_half_cycle;
1110
      reset_half_cycle_flag && reset ##1
1111
         reset_counter > 1;
1112
   endsequence
1113
 
1114
   property p_half_cycle_reset_legal;
1115
      @(clk && enable_a_half_cycle_reset_legal)
1116
          reset_half_cycle_flag |-> s_reset_half_cycle or
1117
                           s_reset_non_half_cycle;
1118
   endproperty
1119
 
1120
   if (USE_BURSTCOUNT >= 0) begin: master_assertion_01
1121
      a_half_cycle_reset_legal: assert property(p_half_cycle_reset_legal)
1122
         else begin
1123
            -> event_a_half_cycle_reset_legal;
1124
            print_assertion("reset must be held accross postive clock edge");
1125
         end
1126
   end
1127
 
1128
   //-------------------------------------------------------------------------------
1129
   // =head3 a_no_read_during_reset
1130
   // This property checks if read is deasserted while reset is asserted
1131
   //-------------------------------------------------------------------------------
1132
 
1133
   property p_no_read_during_reset;
1134
      @(clk && enable_a_no_read_during_reset)
1135
         (reset_counter > 0 || reset_half_cycle_flag) &&
1136
         $rose(clk) |-> !read;
1137
   endproperty
1138
 
1139
   if (USE_READ) begin: master_assertion_02
1140
      a_no_read_during_reset: assert property(p_no_read_during_reset)
1141
         else begin
1142
            -> event_a_no_read_during_reset;
1143
            print_assertion("read must be deasserted while reset is asserted");
1144
         end
1145
   end
1146
 
1147
   //-------------------------------------------------------------------------------
1148
   // =head3 a_no_write_during_reset
1149
   // This property checks if write is deasserted while reset is asserted
1150
   //-------------------------------------------------------------------------------
1151
 
1152
   property p_no_write_during_reset;
1153
      @(clk && enable_a_no_write_during_reset)
1154
         (reset_counter > 0 || reset_half_cycle_flag) &&
1155
         $rose(clk) |-> !write;
1156
      endproperty
1157
 
1158
   if (USE_WRITE) begin: master_assertion_03
1159
      a_no_write_during_reset: assert property(p_no_write_during_reset)
1160
         else begin
1161
            -> event_a_no_write_during_reset;
1162
            print_assertion("write must be deasserted while reset is asserted");
1163
         end
1164
   end
1165
 
1166
   //-------------------------------------------------------------------------------
1167
   // =head3 a_exclusive_read_write
1168
   // This property checks that read and write are not asserted simultaneously
1169
   //-------------------------------------------------------------------------------
1170
 
1171
   property p_exclusive_read_write;
1172
      @(posedge clk && enable_a_exclusive_read_write)
1173
         disable iff (reset || (!clken && (USE_CLKEN)))
1174
         read || write |-> $onehot({read, write});
1175
   endproperty
1176
 
1177
   if (USE_READ && USE_WRITE) begin: master_assertion_04
1178
      a_exclusive_read_write: assert property(p_exclusive_read_write)
1179
         else begin
1180
             -> event_a_exclusive_read_write;
1181
            print_assertion("write and read were asserted simultaneously");
1182
         end
1183
   end
1184
   //-------------------------------------------------------------------------------
1185
   // =head3 a_begintransfer_single_cycle
1186
   // This property checks if begintransfer is asserted for only 1 cycle
1187
   //-------------------------------------------------------------------------------
1188
 
1189
   sequence s_begintransfer_without_waitrequest;
1190
      begintransfer && !waitrequest ##1
1191
         !begintransfer || (begintransfer && (read || write));
1192
   endsequence
1193
 
1194
   sequence s_begintransfer_with_waitrequest;
1195
      begintransfer && waitrequest ##1
1196
         !begintransfer;
1197
   endsequence
1198
 
1199
   property p_begintransfer_single_cycle;
1200
      @(posedge clk && enable_a_begintransfer_single_cycle)
1201
         disable iff (reset || (!clken && (USE_CLKEN)))
1202
         begintransfer |-> s_begintransfer_without_waitrequest or
1203
                           s_begintransfer_with_waitrequest;
1204
   endproperty
1205
 
1206
   if (USE_BEGIN_TRANSFER) begin: master_assertion_05
1207
      a_begintransfer_single_cycle: assert property(p_begintransfer_single_cycle)
1208
         else begin
1209
            -> event_a_begintransfer_single_cycle;
1210
            print_assertion("begintransfer must be asserted for only 1 cycle");
1211
         end
1212
   end
1213
 
1214
   //-------------------------------------------------------------------------------
1215
   // =head3 a_begintransfer_legal
1216
   // This property checks if either read or write is asserted while
1217
   // begintransfer is asserted
1218
   //-------------------------------------------------------------------------------
1219
 
1220
   property p_begintransfer_legal;
1221
      @(posedge clk && enable_a_begintransfer_legal)
1222
         disable iff (reset || (!clken && (USE_CLKEN)))
1223
         begintransfer |-> read || write;
1224
   endproperty
1225
 
1226
   if (USE_BEGIN_TRANSFER) begin: master_assertion_06
1227
      a_begintransfer_legal: assert property(p_begintransfer_legal)
1228
         else begin
1229
            -> event_a_begintransfer_legal;
1230
            print_assertion("neither read nor write was asserted with begintransfer");
1231
         end
1232
   end
1233
 
1234
   //-------------------------------------------------------------------------------
1235
   // =head3 a_begintransfer_exist
1236
   // This property checks if begintransfer is asserted during a transfer
1237
   //-------------------------------------------------------------------------------
1238
 
1239
   property p_begintransfer_exist;
1240
      @(posedge clk && enable_a_begintransfer_exist)
1241
         disable iff (reset || (!clken && (USE_CLKEN)))
1242
         ($rose(read) || $rose(write)) ||
1243
         ((write || read) &&
1244
         (!$fell(waitrequest) && !waitrequested_command_while_clken) &&
1245
         ($rose(waitrequest) || !waitrequest))  |-> begintransfer;
1246
   endproperty
1247
 
1248
   if (USE_BEGIN_TRANSFER) begin: master_assertion_07
1249
      a_begintransfer_exist: assert property(p_begintransfer_exist)
1250
         else begin
1251
            -> event_a_begintransfer_exist;
1252
            print_assertion("begintransfer was deasserted during a transfer");
1253
         end
1254
   end
1255
 
1256
   //-------------------------------------------------------------------------------
1257
   // =head3 a_beginbursttransfer_single_cycle
1258
   // This property checks if beginbursttransfer is asserted for only 1 cycle
1259
   //-------------------------------------------------------------------------------
1260
 
1261
   sequence s_beginbursttransfer_without_waitrequest;
1262
      beginbursttransfer && !waitrequest && write_burst_counter == 0 ##1
1263
         !beginbursttransfer || (beginbursttransfer && (read || write));
1264
   endsequence
1265
 
1266
   sequence s_beginbursttransfer_with_waitrequest;
1267
      beginbursttransfer && waitrequest && write_burst_counter == 0 ##1
1268
         !beginbursttransfer;
1269
   endsequence
1270
 
1271
   property p_beginbursttransfer_single_cycle;
1272
      @(posedge clk && enable_a_beginbursttransfer_single_cycle)
1273
      disable iff (reset || (!clken && (USE_CLKEN)))
1274
         beginbursttransfer |-> s_beginbursttransfer_without_waitrequest or
1275
                                s_beginbursttransfer_with_waitrequest;
1276
   endproperty
1277
 
1278
   if (USE_BEGIN_BURST_TRANSFER) begin: master_assertion_08
1279
      a_beginbursttransfer_single_cycle: assert property(p_beginbursttransfer_single_cycle)
1280
         else begin
1281
            -> event_a_beginbursttransfer_single_cycle;
1282
            print_assertion("beginbursttransfer must be asserted for only 1 cycle");
1283
         end
1284
   end
1285
 
1286
   //-------------------------------------------------------------------------------
1287
   // =head3 a_beginbursttransfer_legal
1288
   // This property checks if either read or write is asserted while
1289
   // beginbursttransfer is asserted
1290
   //-------------------------------------------------------------------------------
1291
 
1292
   property p_beginbursttransfer_legal;
1293
      @(posedge clk && enable_a_beginbursttransfer_legal)
1294
         disable iff (reset || (!clken && (USE_CLKEN)))
1295
         beginbursttransfer |-> read || write;
1296
   endproperty
1297
 
1298
   if (USE_BEGIN_BURST_TRANSFER) begin: master_assertion_09
1299
      a_beginbursttransfer_legal: assert property(p_beginbursttransfer_legal)
1300
         else begin
1301
            -> event_a_beginbursttransfer_legal;
1302
            print_assertion("neither read nor write was asserted with beginbursttransfer");
1303
         end
1304
   end
1305
 
1306
   //-------------------------------------------------------------------------------
1307
   // =head3 a_beginbursttransfer_exist
1308
   // This property checks if beginbursttransfer is asserted during a transfer
1309
   //-------------------------------------------------------------------------------
1310
 
1311
   property p_beginbursttransfer_exist;
1312
      @(posedge clk && enable_a_beginbursttransfer_exist)
1313
         disable iff (reset || (!clken && (USE_CLKEN)))
1314
         (($rose(read) || $rose(write)) ||
1315
         ((write || read) &&
1316
         (!$fell(waitrequest) && !waitrequested_command_while_clken) &&
1317
         ($rose(waitrequest) || !waitrequest))) &&
1318
         write_burst_counter == 0 |-> beginbursttransfer;
1319
   endproperty
1320
 
1321
   if (USE_BEGIN_BURST_TRANSFER) begin: master_assertion_10
1322
      a_beginbursttransfer_exist: assert property(p_beginbursttransfer_exist)
1323
         else begin
1324
            -> event_a_beginbursttransfer_exist;
1325
            print_assertion("beginbursttransfer was deasserted during a transfer");
1326
         end
1327
   end
1328
 
1329
   //------------------------------------------------------------------------------
1330
   // =head3 a_less_than_burstcount_max_size
1331
   // This property checks if burstcount is less than or euqals to maxBurstSize
1332
   //------------------------------------------------------------------------------
1333
 
1334
   property p_less_than_burstcount_max_size;
1335
      @(posedge clk && enable_a_less_than_burstcount_max_size)
1336
         disable iff (reset || (!clken && (USE_CLKEN)))
1337
         burstcount > 0 |-> burstcount <= AV_MAX_BURST;
1338
   endproperty
1339
 
1340
   if (USE_BURSTCOUNT) begin: master_assertion_11
1341
      a_less_than_burstcount_max_size: assert property(p_less_than_burstcount_max_size)
1342
         else begin
1343
            -> event_a_less_than_burstcount_max_size;
1344
            print_assertion("burstcount must be less than or equals to maxBurstSize");
1345
         end
1346
   end
1347
 
1348
   //------------------------------------------------------------------------------
1349
   // =head3 a_byteenable_legal
1350
   // This property checks if byteenalbe is a legal value
1351
   //------------------------------------------------------------------------------
1352
 
1353
   property p_byteenable_legal;
1354
      @(posedge clk && enable_a_byteenable_legal)
1355
         disable iff (reset || (!clken && (USE_CLKEN)))
1356
         byteenable >= 0 |-> byteenable_legal_flag == 0;
1357
      endproperty
1358
 
1359
   if (USE_BYTE_ENABLE) begin: master_assertion_12
1360
      a_byteenable_legal: assert property(p_byteenable_legal)
1361
         else begin
1362
            -> event_a_byteenable_legal;
1363
            print_assertion("byteenable has an illegal value");
1364
         end
1365
   end
1366
 
1367
   //------------------------------------------------------------------------------
1368
   // =head3 a_constant_during_waitrequest
1369
   // This property checks if read, write, writedata, address, burstcount and
1370
   // byteenable are constant while waitrequest is asserted
1371
   //------------------------------------------------------------------------------
1372
 
1373
   sequence s_waitrequest_with_read_constant_in_burst;
1374
      (AV_CONSTANT_BURST_BEHAVIOR) && waitrequest &&
1375
      !$fell(waitrequest) &&
1376
      read ##1 read == $past(read) &&
1377
               address == $past(address) &&
1378
               burstcount == $past(burstcount) &&
1379
               byteenable == $past(byteenable);
1380
   endsequence
1381
 
1382
   sequence s_waitrequest_with_read_inconstant_in_burst;
1383
      !(AV_CONSTANT_BURST_BEHAVIOR) && waitrequest &&
1384
      !$fell(waitrequest) &&
1385
      read ##1 read == $past(read) &&
1386
               $isunknown(address)? $isunknown($past(address)): address == $past(address) &&
1387
               $isunknown(burstcount)? $isunknown($past(burstcount)): burstcount == $past(burstcount) &&
1388
               byteenable == $past(byteenable);
1389
   endsequence
1390
 
1391
   sequence s_waitrequest_with_write_constant_in_burst;
1392
      (AV_CONSTANT_BURST_BEHAVIOR) && waitrequest &&
1393
      !$fell(waitrequest) &&
1394
      write ##1 write == $past(write) &&
1395
                writedata == $past(writedata) &&
1396
                address == $past(address) &&
1397
                burstcount == $past(burstcount) &&
1398
                byteenable == $past(byteenable);
1399
   endsequence
1400
 
1401
   sequence s_waitrequest_with_write_inconstant_in_burst;
1402
      !(AV_CONSTANT_BURST_BEHAVIOR) && waitrequest &&
1403
      !$fell(waitrequest) &&
1404
      write ##1 write == $past(write) &&
1405
                writedata == $past(writedata) &&
1406
                $isunknown(address)? $isunknown($past(address)): address == $past(address) &&
1407
                $isunknown(burstcount)? $isunknown($past(burstcount)): burstcount == $past(burstcount) &&
1408
                byteenable == $past(byteenable);
1409
   endsequence
1410
 
1411
   property p_constant_during_waitrequest;
1412
      @(posedge clk && enable_a_constant_during_waitrequest)
1413
         disable iff (reset || (!clken && (USE_CLKEN)))
1414
         waitrequest &&
1415
         !$fell(waitrequest) &&
1416
         !reset &&
1417
         !$fell(reset) &&
1418
         (read || write) |-> s_waitrequest_with_read_constant_in_burst or s_waitrequest_with_write_constant_in_burst or
1419
                             s_waitrequest_with_read_inconstant_in_burst or s_waitrequest_with_write_inconstant_in_burst;
1420
   endproperty
1421
 
1422
   if (USE_WAIT_REQUEST) begin: master_assertion_13
1423
      a_constant_during_waitrequest:
1424
         assert property(p_constant_during_waitrequest)
1425
         else begin
1426
            -> event_a_constant_during_waitrequest;
1427
            print_assertion("control signal(s) has changed while waitrequest is asserted");
1428
         end
1429
   end
1430
 
1431
   //------------------------------------------------------------------------------
1432
   // =head3 a_constant_during_burst
1433
   // This property checks if address, burstcount are constant
1434
   // during write burst transfer
1435
   //------------------------------------------------------------------------------
1436
 
1437
   property p_constant_during_burst;
1438
      @(posedge clk && enable_a_constant_during_burst)
1439
         disable iff (reset || (!clken && (USE_CLKEN)))
1440
         write_burst_counter > 0 |-> burstcount == $past(burstcount) &&
1441
                                     address == $past(address);
1442
   endproperty
1443
 
1444
   if (USE_BURSTCOUNT && USE_WRITE && AV_CONSTANT_BURST_BEHAVIOR) begin: master_assertion_14
1445
      a_constant_during_burst: assert property(p_constant_during_burst)
1446
         else begin
1447
            -> event_a_constant_during_burst;
1448
            print_assertion("control signal(s) has changed during write burst transfer");
1449
         end
1450
   end
1451
 
1452
   //------------------------------------------------------------------------------
1453
   // =head3 a_burst_legal
1454
   // This property checks if the total number of successive write is asserted and
1455
   // equals to burstcount to complete a write burst transfer
1456
   //------------------------------------------------------------------------------
1457
 
1458
   property p_burst_legal;
1459
      @(posedge clk && enable_a_burst_legal)
1460
         disable iff (reset || (!clken && (USE_CLKEN)))
1461
         (beginbursttransfer || $rose(read)) |-> write_burst_counter == 0;
1462
   endproperty
1463
 
1464
   if (USE_BURSTCOUNT && USE_WRITE &&
1465
      (USE_READ || USE_BEGIN_BURST_TRANSFER)) begin: master_assertion_15
1466
      a_burst_legal: assert property(p_burst_legal)
1467
         else begin
1468
            -> event_a_burst_legal;
1469
            print_assertion("insufficient write were asserted during burst transfer");
1470
         end
1471
   end
1472
 
1473
   //------------------------------------------------------------------------------
1474
   // =head3 a_constant_during_clk_disabled
1475
   // This property checks if all the signals are constant while clken is
1476
   // deasserted.
1477
   //------------------------------------------------------------------------------
1478
 
1479
   sequence s_constant_during_clk_disabled_command;
1480
         clken == 0 ##1 waitrequest === $past(waitrequest) &&
1481
                        burstcount === $past(burstcount) &&
1482
                        address === $past(address) &&
1483
                        waitrequest === $past(waitrequest) &&
1484
                        write === $past(write) &&
1485
                        read === $past(read) &&
1486
                        byteenable === $past(byteenable) &&
1487
                        beginbursttransfer === $past(beginbursttransfer) &&
1488
                        begintransfer === $past(begintransfer) &&
1489
                        writedata === $past(writedata) &&
1490
                        arbiterlock === $past(arbiterlock) &&
1491
                        lock === $past(lock) &&
1492
                        debugaccess === $past(debugaccess)
1493
                        ;
1494
   endsequence
1495
 
1496
   sequence s_constant_during_clk_disabled_response;
1497
         clken == 0 ##0 readdatavalid === $past(readdatavalid) &&
1498
                        readdata === $past(readdata) &&
1499
                        response === $past(response) &&
1500
                        writeresponsevalid === $past(writeresponsevalid)
1501
                        ;
1502
   endsequence
1503
 
1504
   property p_constant_during_clk_disabled;
1505
      @(posedge clk && enable_a_constant_during_clk_disabled)
1506
         disable iff (reset)
1507
         clken == 0 |-> s_constant_during_clk_disabled_response and
1508
                        s_constant_during_clk_disabled_command
1509
                        ;
1510
   endproperty
1511
 
1512
   if (USE_CLKEN) begin: master_assertion_16
1513
      a_constant_during_clk_disabled: assert property(p_constant_during_clk_disabled)
1514
         else begin
1515
            -> event_a_constant_during_clk_disabled;
1516
            print_assertion("signal(s) change while clken is deasserted.");
1517
         end
1518
   end
1519
 
1520
   //------------------------------------------------------------------------------
1521
   // =head3 a_address_align_with_data_width
1522
   // This property checks if master is using byte address, the address must be
1523
   // aligned with the data width.
1524
   //------------------------------------------------------------------------------
1525
 
1526
   property p_address_align_with_data_width;
1527
      @(posedge clk && enable_a_address_align_with_data_width)
1528
         disable iff (reset || (!clken && (USE_CLKEN)))
1529
         ((read || write) && !waitrequest) &&
1530
         (write_burst_counter == 0) |-> (address%AV_NUMSYMBOLS) == 0;
1531
   endproperty
1532
 
1533
   if (USE_ADDRESS && (SLAVE_ADDRESS_TYPE == "SYMBOLS")) begin: master_assertion_17
1534
      a_address_align_with_data_width: assert property(p_address_align_with_data_width)
1535
         else begin
1536
            -> event_a_burst_legal;
1537
            print_assertion("address is not align with data width");
1538
         end
1539
   end
1540
 
1541
   //-------------------------------------------------------------------------------
1542
   // =head2 Slave Assertions
1543
   // The following are the assertions code focus on Slave component checking
1544
   //-------------------------------------------------------------------------------
1545
 
1546
   //-------------------------------------------------------------------------------
1547
   // =head3 a_waitrequest_during_reset
1548
   // This property checks if waitrequest is asserted while reset is asserted
1549
   //-------------------------------------------------------------------------------
1550
 
1551
   property p_waitrequest_during_reset;
1552
      @(clk && enable_a_waitrequest_during_reset)
1553
         (reset_counter > 0 || reset_half_cycle_flag) &&
1554
         ($rose(clk) || $fell(clk)) && !$fell(reset) |-> waitrequest;
1555
   endproperty
1556
 
1557
   if (USE_WAIT_REQUEST) begin: slave_assertion_01
1558
      a_waitrequest_during_reset: assert property(p_waitrequest_during_reset)
1559
         else begin
1560
            -> event_a_waitrequest_during_reset;
1561
            print_assertion("waitrequest must be asserted while reset is asserted");
1562
         end
1563
   end
1564
 
1565
   //-------------------------------------------------------------------------------
1566
   // =head3 a_no_readdatavalid_during_reset
1567
   // This property checks if readdatavalid is deasserted while reset is asserted
1568
   //-------------------------------------------------------------------------------
1569
 
1570
   property p_no_readdatavalid_during_reset;
1571
      @(clk && enable_a_no_readdatavalid_during_reset)
1572
         (reset_counter > 0 || reset_half_cycle_flag) &&
1573
         $rose(clk) |-> !readdatavalid;
1574
   endproperty
1575
 
1576
   if (USE_READ_DATA_VALID) begin: slave_assertion_02
1577
      a_no_readdatavalid_during_reset: assert property(p_no_readdatavalid_during_reset)
1578
         else begin
1579
            -> event_a_no_readdatavalid_during_reset;
1580
            print_assertion("readdatavalid must be deasserted while reset is asserted");
1581
         end
1582
   end
1583
 
1584
   //------------------------------------------------------------------------------
1585
   // =head3 a_less_than_maximumpendingreadtransactions
1586
   // This property checks if pipelined pending read count is less than
1587
   // maximumPendingReadTransaction
1588
   //------------------------------------------------------------------------------
1589
 
1590
   property p_less_than_maximumpendingreadtransactions;
1591
      @(posedge clk && enable_a_less_than_maximumpendingreadtransactions)
1592
         disable iff (reset || (!clken && (USE_CLKEN)))
1593
         pending_read_counter > 0 |->
1594
            pending_read_counter <= (((read && (waitrequest == 1)) || (read && readdatavalid))?
1595
                                    AV_MAX_PENDING_READS+1:AV_MAX_PENDING_READS);
1596
   endproperty
1597
 
1598
   if (USE_READ && USE_READ_DATA_VALID && AV_MAX_PENDING_READS > 0) begin: slave_assertion_03
1599
      a_less_than_maximumpendingreadtransactions:
1600
         assert property(p_less_than_maximumpendingreadtransactions)
1601
         else begin
1602
            -> event_a_less_than_maximumpendingreadtransactions;
1603
            print_assertion("pending read must be within maximumPendingReadTransactions");
1604
         end
1605
   end
1606
 
1607
   //------------------------------------------------------------------------------
1608
   // =head3 a_read_response_sequence
1609
   // This property checks if readdatavalid is asserted while read is asserted for
1610
   // the same read transfer
1611
   //------------------------------------------------------------------------------
1612
 
1613
   sequence s_read_response_sequence_0;
1614
      !read && (readdatavalid_id < read_id) ##1 (round_over == 0);
1615
   endsequence
1616
 
1617
   sequence s_read_response_sequence_1;
1618
      read && ($past(waitrequest) == 1) && ($past(read) == 1) &&
1619
         (readdatavalid_id < read_id-1) ##1 (round_over == 0);
1620
   endsequence
1621
 
1622
   sequence s_read_response_sequence_2;
1623
      ((read && ($past(waitrequest) == 0)) || ($rose(read))) &&
1624
         (readdatavalid_id < read_id) ##1 (round_over == 0);
1625
   endsequence
1626
 
1627
   sequence s_read_response_sequence_3;
1628
      !read && (readdatavalid_id > read_id) ##1 (round_over == 1);
1629
   endsequence
1630
 
1631
   sequence s_read_response_sequence_4;
1632
      read && ($past(waitrequest) == 1) && ($past(read) == 1) &&
1633
         (read_id == 0)?(readdatavalid_id < MAX_ID):(readdatavalid_id > read_id-1) ##1 (round_over == 1);
1634
   endsequence
1635
 
1636
   sequence s_read_response_sequence_5;
1637
      ((read && ($past(waitrequest) == 0)) || ($rose(read))) &&
1638
         (readdatavalid_id > read_id) ##1 (round_over == 1);
1639
   endsequence
1640
 
1641
   property p_read_response_sequence;
1642
      @(posedge clk && enable_a_read_response_sequence)
1643
         disable iff (reset || (!clken && (USE_CLKEN)))
1644
         readdatavalid |-> s_read_response_sequence_0 or
1645
                           s_read_response_sequence_1 or
1646
                           s_read_response_sequence_2 or
1647
                           s_read_response_sequence_3 or
1648
                           s_read_response_sequence_4 or
1649
                           s_read_response_sequence_5;
1650
   endproperty
1651
 
1652
   if (USE_READ_DATA_VALID && USE_READ) begin: slave_assertion_04
1653
      a_read_response_sequence: assert property(p_read_response_sequence)
1654
         else begin
1655
            -> event_a_read_response_sequence;
1656
            print_assertion("readdatavalid must be asserted after read command");
1657
         end
1658
   end
1659
 
1660
   //------------------------------------------------------------------------------
1661
   // =head3 a_readid_sequence
1662
   // This property checks if readid return follow the sequence of transactionid
1663
   // asserted.
1664
   //------------------------------------------------------------------------------
1665
 
1666
   property p_readid_sequence;
1667
      @(posedge clk && enable_a_readid_sequence)
1668
         disable iff (reset || (!clken && (USE_CLKEN)))
1669
         (readdatavalid || ((!USE_READ_DATA_VALID) &&
1670
            (fix_latency_queued_counter == (AV_FIX_READ_LATENCY)))) |->
1671
               readid == temp_read_transactionid_queued;
1672
   endproperty
1673
 
1674
   if (USE_TRANSACTIONID) begin: slave_assertion_05
1675
      a_readid_sequence: assert property(p_readid_sequence)
1676
         else begin
1677
            -> event_a_readid_sequence;
1678
            print_assertion("readid did not match transactionid.");
1679
         end
1680
   end
1681
 
1682
   //------------------------------------------------------------------------------
1683
   // =head3 a_writeid_sequence
1684
   // This property checks if writeid return follow the sequence of transactionid
1685
   // asserted.
1686
   //------------------------------------------------------------------------------
1687
 
1688
   property p_writeid_sequence;
1689
      @(posedge clk && enable_a_writeid_sequence)
1690
         disable iff (reset || (!clken && (USE_CLKEN)))
1691
         writeresponsevalid |-> writeid == temp_write_transactionid_queued;
1692
   endproperty
1693
 
1694
   if (USE_TRANSACTIONID) begin: slave_assertion_06
1695
      a_writeid_sequence: assert property(p_writeid_sequence)
1696
         else begin
1697
            -> event_a_writeid_sequence;
1698
            print_assertion("writeid did not match the transactionid.");
1699
         end
1700
   end
1701
 
1702
   //------------------------------------------------------------------------------
1703
   // =head3 a_register_incoming_signals
1704
   // This property checks if waitrequest is asserted all the times except
1705
   // deasserted at the single clock cycle after read/write transaction happen.
1706
   //------------------------------------------------------------------------------
1707
 
1708
   sequence s_register_incoming_signals_with_waitrequested_command;
1709
      ((read && waitrequest) || (write && waitrequest)) ##[1:$] !waitrequest ##1 waitrequest;
1710
   endsequence
1711
 
1712
   sequence s_register_incoming_signals_without_command;
1713
      (!write && !read) ##0 waitrequest;
1714
   endsequence
1715
 
1716
   sequence s_register_incoming_signals_read;
1717
      (read && !waitrequest) ##0 (read === $past(read) && $past(waitrequest) == 1) ##1
1718
            waitrequest;
1719
   endsequence
1720
 
1721
   sequence s_register_incoming_signals_write;
1722
      (write && !waitrequest) ##0 (write === $past(write) && $past(waitrequest) == 1) ##1
1723
            waitrequest;
1724
   endsequence
1725
 
1726
   property p_register_incoming_signals;
1727
      @(posedge clk && enable_a_register_incoming_signals)
1728
         disable iff (!clken && (USE_CLKEN))
1729
         enable_a_register_incoming_signals |-> s_register_incoming_signals_read or
1730
         s_register_incoming_signals_write or
1731
         s_register_incoming_signals_without_command or
1732
         s_register_incoming_signals_with_waitrequested_command;
1733
   endproperty
1734
 
1735
   if (AV_REGISTERINCOMINGSIGNALS) begin: slave_assertion_07
1736
      a_register_incoming_signals:
1737
         assert property(p_register_incoming_signals)
1738
         else begin
1739
            -> event_a_register_incoming_signals;
1740
            print_assertion("waitrequest not asserted in first cycle of transaction.");
1741
         end
1742
   end
1743
 
1744
   //------------------------------------------------------------------------------
1745
   // =head3 a_unrequested_write_response
1746
   // This property checks for write response to occur only when there is
1747
   // request for write response
1748
   //------------------------------------------------------------------------------
1749
 
1750
   property p_unrequested_write_response;
1751
      @(posedge clk && enable_a_unrequested_write_response)
1752
         disable iff (reset || (!clken && (USE_CLKEN)))
1753
         pending_write_response == 0 |-> !writeresponsevalid;
1754
   endproperty
1755
 
1756
   if (USE_WRITE && USE_WRITERESPONSE) begin: slave_assertion_08
1757
      a_unrequested_write_response: assert property(p_unrequested_write_response)
1758
         else begin
1759
            -> event_a_unrequested_write_response;
1760
            print_assertion("write response must only happen when write response is requested");
1761
         end
1762
   end
1763
   //-------------------------------------------------------------------------------
1764
   // =head2 Timeout Assertions
1765
   // The following are the assertions code focus on timeout checking
1766
   //-------------------------------------------------------------------------------
1767
 
1768
   //------------------------------------------------------------------------------
1769
   // =head3 a_write_burst_timeout
1770
   // This property checks if write burst transfer is completed within timeout
1771
   // period
1772
   //------------------------------------------------------------------------------
1773
 
1774
   property p_write_burst_timeout;
1775
      @(posedge clk && enable_a_write_burst_timeout)
1776
         disable iff (reset || (!clken && (USE_CLKEN)))
1777
         write_burst_counter > 0 |->
1778
            write_burst_timeout_counter <= AV_WRITE_TIMEOUT;
1779
   endproperty
1780
 
1781
   if (USE_BURSTCOUNT && USE_WRITE && AV_WRITE_TIMEOUT > 0) begin: timeout_assertion_01
1782
      a_write_burst_timeout: assert property(p_write_burst_timeout)
1783
         else begin
1784
            -> event_a_write_burst_timeout;
1785
            print_assertion("write burst transfer must be completed within timeout period");
1786
         end
1787
   end
1788
 
1789
   //------------------------------------------------------------------------------
1790
   // =head3 a_waitrequest_timeout
1791
   // This property checks if waitrequest is asserted continously for more than
1792
   // maximum allowed timeout period
1793
   //------------------------------------------------------------------------------
1794
 
1795
   property p_waitrequest_timeout;
1796
      @(posedge clk && enable_a_waitrequest_timeout)
1797
         waitrequest_timeout_counter > 0 |->
1798
            waitrequest_timeout_counter <= AV_WAITREQUEST_TIMEOUT;
1799
   endproperty
1800
 
1801
   if (USE_WAIT_REQUEST && AV_WAITREQUEST_TIMEOUT > 0) begin: timeout_assertion_02
1802
      a_waitrequest_timeout: assert property(p_waitrequest_timeout)
1803
         else begin
1804
            -> event_a_waitrequest_timeout;
1805
            print_assertion("continuous waitrequest must be within timeout period");
1806
         end
1807
   end
1808
 
1809
   //------------------------------------------------------------------------------
1810
   // =head3 a_read_response_timeout
1811
   // This property checks if readdatavalid is asserted within timeout period
1812
   // =cut
1813
   //------------------------------------------------------------------------------
1814
 
1815
   property p_read_response_timeout;
1816
      @(posedge clk && enable_a_read_response_timeout)
1817
         disable iff (reset || (!clken && (USE_CLKEN)))
1818
         temp_read_response_timeout_counter[readdatavalid_id] > 0 |->
1819
            temp_read_response_timeout_counter[readdatavalid_id] <= AV_READ_TIMEOUT;
1820
   endproperty
1821
 
1822
   if (USE_READ && USE_READ_DATA_VALID && AV_READ_TIMEOUT > 0) begin: timeout_assertion_03
1823
      a_read_response_timeout: assert property(p_read_response_timeout)
1824
         else begin
1825
            -> event_a_read_response_timeout;
1826
            print_assertion("readdatavalid must be asserted within timeout period");
1827
         end
1828
   end
1829
 
1830
   //------------------------------------------------------------------------------
1831
   // =head3 a_write_response_timeout
1832
   // This property checks if write response happens within timeout
1833
   // period after completed write command
1834
   //------------------------------------------------------------------------------
1835
 
1836
   property p_write_response_timeout;
1837
      @(posedge clk && enable_a_write_response_timeout)
1838
         disable iff (reset || (!clken && (USE_CLKEN)))
1839
         write_response_timeout_counter[0] > 0 |->
1840
            write_response_timeout_counter[0] <= write_response_timeout;
1841
   endproperty
1842
 
1843
   if (USE_WRITE && USE_WRITERESPONSE > 0) begin: timeout_assertion_04
1844
      a_write_response_timeout: assert property(p_write_response_timeout)
1845
         else begin
1846
            -> event_a_write_response_timeout;
1847
            print_assertion("write response must happens within timeout period after completed write command");
1848
         end
1849
   end
1850
 
1851
   //--------------------------------------------------------------------------
1852
   // ASSERTION CODE END
1853
   //--------------------------------------------------------------------------
1854
   `endif
1855
 
1856
   // synthesis translate_on
1857
 
1858
endmodule

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