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[/] [qaz_libs/] [trunk/] [avalon_lib/] [sim/] [src/] [amm_monitor/] [altera_avalon_mm_monitor_coverage.sv] - Blame information for rev 31

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// (C) 2001-2016 Intel Corporation. All rights reserved.
2
// Your use of Intel Corporation's design tools, logic functions and other
3
// software and tools, and its AMPP partner logic functions, and any output
4
// files any of the foregoing (including device programming or simulation
5
// files), and any associated documentation or information are expressly subject
6
// to the terms and conditions of the Intel Program License Subscription
7
// Agreement, Intel MegaCore Function License Agreement, or other applicable
8
// license agreement, including, without limitation, that your use is for the
9
// sole purpose of programming logic devices manufactured by Intel and sold by
10
// Intel or its authorized distributors.  Please refer to the applicable
11
// agreement for further details.
12
 
13
 
14
// $File: //acds/rel/16.1/ip/sopc/components/verification/altera_avalon_mm_monitor_bfm/altera_avalon_mm_monitor_coverage.sv $
15
// $Revision: #1 $
16
// $Date: 2016/08/07 $
17
//-----------------------------------------------------------------------------
18
// =head1 NAME
19
// altera_avalon_mm_monitor_coverage
20
// =head1 SYNOPSIS
21
// Memory Mapped Avalon Bus Protocol Checker
22
//-----------------------------------------------------------------------------
23
// =head1 DESCRIPTION
24
// This module implements Avalon MM protocol coverage for simulation.
25
//-----------------------------------------------------------------------------
26
 
27
`timescale 1ps / 1ps
28
 
29
module altera_avalon_mm_monitor_coverage(
30
                                         clk,
31
                                         reset,
32
                                         tap
33
                                        );
34
 
35
   // =head1 PARAMETERS
36
   parameter AV_ADDRESS_W               = 32;   // address width
37
   parameter AV_SYMBOL_W                = 8;    // default symbol is byte
38
   parameter AV_NUMSYMBOLS              = 4;    // number of symbols per word
39
   parameter AV_BURSTCOUNT_W            = 3;    // burst port width
40
 
41
   parameter AV_BURST_LINEWRAP          = 0;    // line wrapping addr is set to 1
42
   parameter AV_BURST_BNDR_ONLY         = 0;    // addr is multiple of burst size
43
   parameter REGISTER_WAITREQUEST       = 0;    // Waitrequest is registered at the slave
44
   parameter AV_MAX_PENDING_READS       = 1;    // maximum pending read transfer count
45
   parameter AV_MAX_PENDING_WRITES      = 0;    // maximum pending write transfer count
46
   parameter AV_FIX_READ_LATENCY        = 0;    // fixed read latency in cycles
47
 
48
   parameter USE_READ                   = 1;    // use read port
49
   parameter USE_WRITE                  = 1;    // use write port
50
   parameter USE_ADDRESS                = 1;    // use address port
51
   parameter USE_BYTE_ENABLE            = 1;    // use byteenable port
52
   parameter USE_BURSTCOUNT             = 0;    // use burstcount port
53
   parameter USE_READ_DATA              = 1;    // use readdata port
54
   parameter USE_READ_DATA_VALID        = 1;    // use readdatavalid port
55
   parameter USE_WRITE_DATA             = 1;    // use writedata port
56
   parameter USE_BEGIN_TRANSFER         = 0;    // use begintransfer port
57
   parameter USE_BEGIN_BURST_TRANSFER   = 0;    // use begintbursttransfer port
58
   parameter USE_WAIT_REQUEST           = 1;    // use waitrequest port
59
   parameter USE_ARBITERLOCK            = 0;    // Use arbiterlock pin on interface
60
   parameter USE_LOCK                   = 0;    // Use lock pin on interface
61
   parameter USE_DEBUGACCESS            = 0;    // Use debugaccess pin on interface
62
   parameter USE_TRANSACTIONID          = 0;    // Use transactionid interface pin
63
   parameter USE_WRITERESPONSE          = 0;    // Use write response interface pins
64
   parameter USE_READRESPONSE           = 0;    // Use read response interface pins
65
   parameter USE_CLKEN                  = 0;    // Use clken interface pins
66
 
67
   parameter AV_MAX_READ_LATENCY             = 100;   // maximum read latency cycle for coverage
68
   parameter AV_MAX_WAITREQUESTED_READ       = 100;   // maximum waitrequested read cycle for coverage
69
   parameter AV_MAX_WAITREQUESTED_WRITE      = 100;   // maximum waitrequested write cycle for coverage
70
   parameter AV_MAX_CONTINUOUS_READ          = 5;   // maximum continuous read cycle for coverage
71
   parameter AV_MAX_CONTINUOUS_WRITE         = 5;   // maximum continuous write cycle for coverage
72
   parameter AV_MAX_CONTINUOUS_WAITREQUEST   = 5;   // maximum continuous waitrequest cycle for coverage
73
   parameter AV_MAX_CONTINUOUS_READDATAVALID = 5;   // maximum continuous readdatavalid cycle for coverage
74
 
75
   parameter AV_READ_WAIT_TIME         = 0;  // Fixed wait time cycles when
76
   parameter AV_WRITE_WAIT_TIME        = 0;  // USE_WAIT_REQUEST is 0
77
 
78
   localparam AV_DATA_W = AV_SYMBOL_W * AV_NUMSYMBOLS;
79
   localparam AV_MAX_BURST = USE_BURSTCOUNT ? 2**(lindex(AV_BURSTCOUNT_W)) : 1;
80
   localparam INT_WIDTH = 32;
81
   localparam MAX_ID = (AV_MAX_PENDING_READS*AV_MAX_BURST > 100? AV_MAX_PENDING_READS*AV_MAX_BURST:100);
82
   localparam AV_TRANSACTIONID_W = 8;
83
 
84
   localparam TAP_W = 1 +                                                  // clken
85
                      1 +                                                  // arbiterlock
86
                      1 +                                                  // lock
87
                      1 +                                                  // debugaccess
88
                      ((AV_TRANSACTIONID_W == 0)? 1:AV_TRANSACTIONID_W) +  // transactionid
89
                      ((AV_TRANSACTIONID_W == 0)? 1:AV_TRANSACTIONID_W) +  // readid
90
                      ((AV_TRANSACTIONID_W == 0)? 1:AV_TRANSACTIONID_W) +  // writeid
91
                      2 +                                                  // response
92
                      1 +                                                  // writeresponserequest
93
                      1 +                                                  // writeresponsevalid
94
                      1 +                                                  // waitrequest
95
                      1 +                                                  // readdatavalid
96
                      ((AV_DATA_W == 0)? 1:AV_DATA_W) +                    // readdata
97
                      1 +                                                  // write
98
                      1 +                                                  // read
99
                      ((AV_ADDRESS_W == 0)? 1:AV_ADDRESS_W) +              // address
100
                      ((AV_NUMSYMBOLS == 0)? 1:AV_NUMSYMBOLS) +            // byteenable
101
                      ((AV_BURSTCOUNT_W == 0)? 1:AV_BURSTCOUNT_W) +        // burstcount
102
                      1 +                                                  // beginbursttransfer
103
                      1 +                                                  // begintransfer
104
                      ((AV_DATA_W == 0)? 1:AV_DATA_W);                     // writedata
105
 
106
   // =head1 PINS
107
   // =head2 Clock Interface
108
   input                                             clk;
109
   input                                             reset;
110
 
111
   // =head2 Avalon Monitor Interface
112
   // Interface consists of Avalon Memory-Mapped Interface.
113
   // =cut
114
 
115
   // =pod
116
   input  [TAP_W-1:0]                                tap;
117
   // =cut
118
 
119
   function int lindex;
120
      // returns the left index for a vector having a declared width
121
      // when width is 0, then the left index is set to 0 rather than -1
122
      input [31:0] width;
123
      lindex = (width > 0) ? (width-1) : 0;
124
   endfunction
125
 
126
   function automatic int __floor1(
127
      bit [31:0] arg
128
   );
129
      __floor1 = (arg <1) ? 1 : arg;
130
   endfunction
131
 
132
   //--------------------------------------------------------------------------
133
   // synthesis translate_off
134
 
135
   import verbosity_pkg::*;
136
   import avalon_mm_pkg::*;
137
 
138
   typedef bit [lindex(AV_ADDRESS_W):0]                    AvalonAddress_t;
139
   typedef bit [lindex(AV_BURSTCOUNT_W):0]                 AvalonBurstCount_t;
140
   typedef bit [AV_MAX_BURST-1:0][AV_DATA_W-1:0]     AvalonData_t;
141
   typedef bit [AV_MAX_BURST-1:0][AV_NUMSYMBOLS-1:0] AvalonByteEnable_t;
142
   typedef bit [AV_MAX_BURST-1:0][INT_WIDTH-1:0]     AvalonLatency_t;
143
   typedef bit [AV_MAX_BURST-1:0][1:0]               AvalonReadResponseStatus_t;
144
 
145
   typedef struct packed {
146
                          Request_t                  request;
147
                          AvalonAddress_t            address;     // start address
148
                          AvalonBurstCount_t         burst_count; // burst length
149
                          AvalonData_t               data;        // write data
150
                          AvalonByteEnable_t         byte_enable; // hot encoded
151
                          int                        burst_cycle;
152
                          logic                      write_response_request;
153
                         } SlaveCommand_t;
154
 
155
   typedef struct packed {
156
                          Request_t                  request;
157
                          AvalonAddress_t            address;     // start addr
158
                          AvalonBurstCount_t         burst_count; // burst length
159
                          AvalonData_t               data;        // read data
160
                          AvalonLatency_t            read_latency;
161
                          AvalonLatency_t            wait_latency;
162
                          AvalonReadResponseStatus_t read_response;
163
                          AvalonResponseStatus_t     write_response;
164
                         } MasterResponse_t;
165
 
166
 
167
   string                        message       = "*unitialized*";
168
 
169
   bit                           covergroup_settings_changed_flag = 0;
170
   bit [1:0]                     reset_flag = 2'b11;
171
   bit                           read_transaction_flag = 0;
172
   bit                           read_without_waitrequest_flag = 0;
173
   bit                           idle_write_flag = 0;
174
   logic [MAX_ID:0]              idle_read_flag = 0;
175
   bit                           idle_in_write_burst_flag = 0;
176
   logic [MAX_ID:0]              read_latency_start_flag = 0;
177
 
178
   bit                           enable_c_read_byteenable = 1;
179
   bit                           enable_c_write_byteenable = 1;
180
   bit                           enable_c_read_burstcount = 1;
181
   bit                           enable_c_write_burstcount = 1;
182
   bit                           enable_c_pending_read = 1;
183
   bit                           enable_c_read = 1;
184
   bit                           enable_c_write = 1;
185
   bit                           enable_c_b2b_read_read = 1;
186
   bit                           enable_c_b2b_read_write = 1;
187
   bit                           enable_c_b2b_write_write = 1;
188
   bit                           enable_c_b2b_write_read = 1;
189
   bit                           enable_c_idle_in_write_burst = 1;
190
   bit                           enable_c_idle_in_read_response = 1;
191
   bit                           enable_c_read_latency = 1;
192
   bit                           enable_c_waitrequested_read = 1;
193
   bit                           enable_c_waitrequested_write = 1;
194
   bit                           enable_c_continuous_waitrequest_from_idle_to_write = 1;
195
   bit                           enable_c_continuous_waitrequest_from_idle_to_read = 1;
196
   bit                           enable_c_waitrequest_without_command = 1;
197
   bit                           enable_c_idle_before_transaction = 1;
198
   bit                           enable_c_continuous_read = 1;
199
   bit                           enable_c_continuous_write = 1;
200
   bit                           enable_c_continuous_readdatavalid = 1;
201
   bit                           enable_c_continuous_waitrequest = 1;
202
   bit                           enable_c_waitrequest_in_write_burst = 1;
203
   bit                           enable_c_readresponse = 0;
204
   bit                           enable_c_writeresponse = 0;
205
   bit                           enable_c_write_after_reset = 1;
206
   bit                           enable_c_read_after_reset = 1;
207
   bit                           enable_c_write_response = 1;
208
   bit                           enable_c_read_response = 1;
209
   bit                           enable_c_write_response_transition = 1;
210
   bit                           enable_c_read_response_transition = 1;
211
 
212
   int                           read_command_while_clken = 0;
213
   int                           write_command_while_clken = 0;
214
   int                           waitrequested_command_while_clken = 0;
215
   int                           write_burst_counter = 0;
216
   logic [MAX_ID:0][31:0]        read_burst_counter = 0;
217
   int                           temp_read_burst_counter = 0;
218
   int                           pending_read_counter = 0;
219
   int                           fix_read_latency_counter = 0;
220
   int                           idle_in_read_response = 0;
221
   logic [MAX_ID:0][31:0]        temp_idle_in_read_response = 0;
222
   int                           temp_waitrequested_read_counter = 0;
223
   int                           waitrequested_read_counter = 0;
224
   int                           temp_waitrequested_write_counter = 0;
225
   int                           waitrequested_write_counter = 0;
226
   int                           byteenable_counter = 0;
227
   logic [MAX_ID:0][31:0]        temp_read_latency_counter = 0;
228
   int                           read_latency_counter = 0;
229
   int                           read_id = 0;
230
   int                           readdatavalid_id = 0;
231
   bit                           waitrequest_before_waitrequested_read = 0;
232
   bit                           waitrequest_before_waitrequested_write = 0;
233
   bit                           waitrequest_before_command = 0;
234
   bit                           waitrequest_without_command = 0;
235
   logic                         past_waitrequest = 0;
236
   logic                         idle_before_burst_transaction = 0;
237
   logic                         idle_before_burst_transaction_sampled = 0;
238
   logic                         continuous_read_sampled = 0;
239
   logic                         continuous_read_start_flag = 0;
240
   logic [31:0]                  continuous_read = 0;
241
   logic                         continuous_write_sampled = 0;
242
   logic                         continuous_write_start_flag = 0;
243
   logic [31:0]                  continuous_write = 0;
244
   logic                         continuous_readdatavalid_sampled = 0;
245
   logic                         continuous_readdatavalid_start_flag = 0;
246
   logic [31:0]                  continuous_readdatavalid = 0;
247
   logic                         continuous_waitrequest_sampled = 0;
248
   logic                         continuous_waitrequest_start_flag = 0;
249
   logic [31:0]                  continuous_waitrequest = 0;
250
   logic                         idle_in_write_burst_with_waitrequest = 0;
251
   logic                         idle_in_write_burst_with_waitrequest_sampled = 0;
252
   logic                         idle_in_write_burst_start_flag = 0;
253
   logic                         idle_before_burst_transaction_with_waitrequest = 0;
254
   logic                         idle_before_burst_transaction_with_waitrequest_sampled = 0;
255
   logic [31:0]                  waitrequested_before_transaction = 0;
256
   logic                         write_after_reset = 0;
257
   logic                         read_after_reset = 0;
258
   int                           fix_latency_queued[$];
259
   int                           fix_latency_queued_counter = 0;
260
   logic                         read_reset_transaction = 0;
261
   logic                         write_reset_transaction = 0;
262
   logic                         burst_waitrequested_command = 0;
263
   logic [31:0]                  readresponse_bit_num = 0;
264
   logic [31:0]                  writeresponse_bit_num = 0;
265
   AvalonResponseStatus_t        read_response;
266
   AvalonResponseStatus_t        write_response;
267
   logic [3:0]                   write_response_transition = 4'bx;
268
   logic [3:0]                   read_response_transition = 4'bx;
269
 
270
   logic [3:0]                   b2b_transfer = 4'b1111;
271
   logic [AV_NUMSYMBOLS-1:0]     check_byteenable = 0;
272
   logic [AV_NUMSYMBOLS-1:0]     legal_byteenable[(AV_NUMSYMBOLS*2)-1:0];
273
 
274
   logic                         byteenable_1_bit = 1'b1;
275
   logic [1:0]                   byteenable_2_bit = 2'b11;
276
   logic [3:0]                   byteenable_4_bit = 4'hf;
277
   logic [7:0]                   byteenable_8_bit = 8'hff;
278
   logic [15:0]                  byteenable_16_bit = 16'hffff;
279
   logic [31:0]                  byteenable_32_bit = 32'hffffffff;
280
   logic [63:0]                  byteenable_64_bit = 64'hffffffffffffffff;
281
   logic [127:0]                 byteenable_128_bit = 128'hffffffffffffffffffffffffffffffff;
282
 
283
   //--------------------------------------------------------------------------
284
   // unpack Avalon bus interface tap into individual port signals
285
 
286
   logic                                  waitrequest;
287
   logic                                  readdatavalid;
288
   logic [lindex(AV_DATA_W):0]            readdata;
289
   logic                                  write;
290
   logic                                  read;
291
   logic [lindex(AV_ADDRESS_W):0]         address;
292
   logic [31:0]                           byteenable;
293
   logic [lindex(AV_BURSTCOUNT_W):0]      burstcount;
294
   logic                                  beginbursttransfer;
295
   logic                                  begintransfer;
296
   logic [lindex(AV_DATA_W):0]            writedata;
297
 
298
   logic                                  arbiterlock;
299
   logic                                  lock;
300
   logic                                  debugaccess;
301
 
302
   logic [lindex(AV_TRANSACTIONID_W):0]   transactionid;
303
   logic [lindex(AV_TRANSACTIONID_W):0]   readid;
304
   logic [lindex(AV_TRANSACTIONID_W):0]   writeid;
305
   logic [1:0]                            response;
306
   logic                                  writeresponserequest;
307
   logic                                  writeresponsevalid;
308
   logic                                  clken;
309
 
310
   always_comb begin
311
      clken <= (USE_CLKEN == 1)?
312
                      tap[3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+21:
313
                          3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+21] : 1;
314
 
315
      arbiterlock <= (USE_ARBITERLOCK == 1)?
316
                      tap[3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+20:
317
                          3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+20] : 0;
318
 
319
      lock <= (USE_LOCK == 1)?
320
                      tap[3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+19:
321
                          3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+19] : 0;
322
 
323
      debugaccess <= (USE_DEBUGACCESS == 1)?
324
                      tap[3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+18:
325
                          3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+18] : 0;
326
 
327
      transactionid <= (USE_TRANSACTIONID == 1)?
328
                      tap[3*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+17:
329
                          2*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+17] : 0;
330
 
331
      readid <= (USE_READRESPONSE == 1)?
332
                      tap[2*(lindex(AV_TRANSACTIONID_W))+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+16:
333
                          lindex(AV_TRANSACTIONID_W)+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+16] : 0;
334
 
335
      writeid <= (USE_WRITERESPONSE == 1)?
336
                      tap[lindex(AV_TRANSACTIONID_W)+2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+15:
337
                          2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+15] : 0;
338
 
339
      response <= (USE_WRITERESPONSE == 1 || USE_READRESPONSE == 1)?
340
                 tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+14:
341
                     2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+13] : 0;
342
 
343
      writeresponserequest <= (USE_WRITERESPONSE == 1)?
344
                      tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+12:
345
                          2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+12] : 0;
346
 
347
      writeresponsevalid <= (USE_WRITERESPONSE == 1)?
348
                      tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+11:
349
                          2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+11] : 0;
350
 
351
      waitrequest <= tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+10:
352
                          2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+10];
353
 
354
      readdatavalid <= (USE_READ_DATA_VALID == 1)?
355
                        tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+9:
356
                            2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+9] : 0;
357
 
358
      readdata <= (USE_READ_DATA == 1)?
359
                   tap[2*(lindex(AV_DATA_W))+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+8:
360
                       lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+8] : 0;
361
 
362
      write <= (USE_WRITE == 1)?
363
                tap[lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+7:
364
                    lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+7] : 0;
365
 
366
      read <= (USE_READ == 1)?
367
               tap[lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+6:
368
                   lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+6] : 0;
369
 
370
      address <= (USE_ADDRESS == 1)?
371
                  tap[lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+lindex(AV_ADDRESS_W)+5:
372
                      lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+5] : 0;
373
 
374
      byteenable <= (USE_BYTE_ENABLE == 1)?
375
                     tap[lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+lindex(AV_NUMSYMBOLS)+4:
376
                         lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+4] : 0;
377
 
378
      burstcount <= (USE_BURSTCOUNT == 1)?
379
                     tap[lindex(AV_DATA_W)+lindex(AV_BURSTCOUNT_W)+3: lindex(AV_DATA_W)+3] : 1;
380
 
381
      beginbursttransfer <= (USE_BEGIN_BURST_TRANSFER == 1)?
382
                             tap[lindex(AV_DATA_W)+2:lindex(AV_DATA_W)+2] : 0;
383
 
384
      begintransfer <= (USE_BEGIN_TRANSFER == 1)? tap[lindex(AV_DATA_W)+1:lindex(AV_DATA_W)+1] : 0;
385
 
386
      writedata <= (USE_WRITE_DATA == 1)? tap[lindex(AV_DATA_W):0] : 0;
387
   end
388
 
389
   //--------------------------------------------------------------------------
390
   // =head1 Public Methods API
391
   // This section describes the public methods in the application programming
392
   // interface (API). In this case the application program is the test bench
393
   // which instantiates and controls and queries state of this component.
394
   // Test programs must only use these public access methods and events to
395
   // communicate with this BFM component. The API and the module pins
396
   // are the only interfaces in this component that are guaranteed to be
397
   // stable. The API will be maintained for the life of the product.
398
   // While we cannot prevent a test program from directly accessing internal
399
   // tasks, functions, or data private to the BFM, there is no guarantee that
400
   // these will be present in the future. In fact, it is best for the user
401
   // to assume that the underlying implementation of this component can
402
   // and will change.
403
   // =cut
404
   //--------------------------------------------------------------------------
405
 
406
   // Master Coverages API
407
   function automatic void set_enable_c_read_byteenable( // public
408
      bit     cover_enable
409
   );
410
      // enable or disable c_read_byteenable cover group
411
 
412
      enable_c_read_byteenable = cover_enable;
413
      coverage_settings_check(covergroup_settings_changed_flag, "c_read_byteenable");
414
   endfunction
415
 
416
   function automatic void set_enable_c_write_byteenable( // public
417
      bit     cover_enable
418
   );
419
      // enable or disable c_write_byteenable cover group
420
 
421
      enable_c_write_byteenable = cover_enable;
422
      coverage_settings_check(covergroup_settings_changed_flag, "c_write_byteenable");
423
   endfunction
424
 
425
   function automatic void set_enable_c_read_burstcount( // public
426
      bit     cover_enable
427
   );
428
      // enable or disable c_read_burstcount cover group
429
 
430
      enable_c_read_burstcount = cover_enable;
431
      coverage_settings_check(covergroup_settings_changed_flag, "c_read_burstcount");
432
   endfunction
433
 
434
   function automatic void set_enable_c_write_burstcount( // public
435
      bit     cover_enable
436
   );
437
      // enable or disable c_write_burstcount cover group
438
 
439
      enable_c_write_burstcount = cover_enable;
440
      coverage_settings_check(covergroup_settings_changed_flag, "c_write_burstcount");
441
   endfunction
442
 
443
   function automatic void set_enable_c_pending_read( // public
444
      bit     cover_enable
445
   );
446
      // enable or disable c_pending_read cover group
447
 
448
      enable_c_pending_read = cover_enable;
449
      coverage_settings_check(covergroup_settings_changed_flag, "c_pending_read");
450
   endfunction
451
 
452
   function automatic void set_enable_c_read( // public
453
      bit     cover_enable
454
   );
455
      // enable or disable c_read cover group
456
 
457
      enable_c_read = cover_enable;
458
      coverage_settings_check(covergroup_settings_changed_flag, "c_read");
459
   endfunction
460
 
461
   function automatic void set_enable_c_write( // public
462
      bit     cover_enable
463
   );
464
      // enable or disable c_write cover group
465
 
466
      enable_c_write = cover_enable;
467
      coverage_settings_check(covergroup_settings_changed_flag, "c_write");
468
   endfunction
469
 
470
   function automatic void set_enable_c_b2b_read_read( // public
471
      bit     cover_enable
472
   );
473
      // enable or disable c_b2b_read_read cover group
474
 
475
      enable_c_b2b_read_read = cover_enable;
476
      coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_read_read");
477
   endfunction
478
 
479
   function automatic void set_enable_c_b2b_read_write( // public
480
      bit     cover_enable
481
   );
482
      // enable or disable c_b2b_read_write cover group
483
 
484
      enable_c_b2b_read_write = cover_enable;
485
      coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_read_write");
486
   endfunction
487
 
488
   function automatic void set_enable_c_b2b_write_write( // public
489
      bit     cover_enable
490
   );
491
      // enable or disable c_b2b_write_write cover group
492
 
493
      enable_c_b2b_write_write = cover_enable;
494
      coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_write_write");
495
   endfunction
496
 
497
   function automatic void set_enable_c_b2b_write_read( // public
498
      bit     cover_enable
499
   );
500
      // enable or disable c_b2b_write_read cover group
501
 
502
      enable_c_b2b_write_read = cover_enable;
503
      coverage_settings_check(covergroup_settings_changed_flag, "c_b2b_write_read");
504
   endfunction
505
 
506
   function automatic void set_enable_c_idle_in_write_burst( // public
507
      bit     cover_enable
508
   );
509
      // enable or disable c_idle_in_write_burst cover group
510
 
511
      enable_c_idle_in_write_burst = cover_enable;
512
      coverage_settings_check(covergroup_settings_changed_flag, "c_idle_in_write_burst");
513
   endfunction
514
 
515
   // Slave Coverages API
516
   function automatic void set_enable_c_idle_in_read_response( // public
517
      bit     cover_enable
518
   );
519
      // enable or disable c_idle_in_read_response cover group
520
 
521
      enable_c_idle_in_read_response = cover_enable;
522
      coverage_settings_check(covergroup_settings_changed_flag, "c_idle_in_read_response");
523
   endfunction
524
 
525
   function automatic void set_enable_c_read_latency( // public
526
      bit     cover_enable
527
   );
528
      // enable or disable c_read_latency cover group
529
 
530
      enable_c_read_latency = cover_enable;
531
      coverage_settings_check(covergroup_settings_changed_flag, "c_read_latency");
532
   endfunction
533
 
534
   function automatic void set_enable_c_waitrequested_read( // public
535
      bit     cover_enable
536
   );
537
      // enable or disable c_waitrequested_read cover group
538
 
539
      enable_c_waitrequested_read = cover_enable;
540
      coverage_settings_check(covergroup_settings_changed_flag, "c_waitrequested_read");
541
   endfunction
542
 
543
   function automatic void set_enable_c_waitrequested_write( // public
544
      bit     cover_enable
545
   );
546
      // enable or disable c_waitrequested_write cover group
547
 
548
      enable_c_waitrequested_write = cover_enable;
549
      coverage_settings_check(covergroup_settings_changed_flag, "c_waitrequested_write");
550
   endfunction
551
 
552
   function automatic void set_enable_c_continuous_waitrequest_from_idle_to_write( // public
553
      bit     cover_enable
554
   );
555
      // enable or disable c_continuous_waitrequest_from_idle_to_write cover group
556
 
557
      enable_c_continuous_waitrequest_from_idle_to_write = cover_enable;
558
      coverage_settings_check(covergroup_settings_changed_flag, "c_continuous_waitrequest_from_idle_to_write");
559
   endfunction
560
 
561
   function automatic void set_enable_c_continuous_waitrequest_from_idle_to_read( // public
562
      bit     cover_enable
563
   );
564
      // enable or disable c_continuous_waitrequest_from_idle_to_read cover group
565
 
566
      enable_c_continuous_waitrequest_from_idle_to_read = cover_enable;
567
      coverage_settings_check(covergroup_settings_changed_flag, "c_continuous_waitrequest_from_idle_to_read");
568
   endfunction
569
 
570
   function automatic void set_enable_c_waitrequest_without_command( // public
571
      bit     cover_enable
572
   );
573
      // enable or disable c_waitrequest_without_command cover group
574
 
575
      enable_c_waitrequest_without_command = cover_enable;
576
      coverage_settings_check(covergroup_settings_changed_flag, "c_waitrequest_without_command");
577
   endfunction
578
 
579
   function automatic void set_enable_c_idle_before_transaction( // public
580
      bit     cover_enable
581
   );
582
      // enable or disable c_idle_before_transaction cover group
583
 
584
      enable_c_idle_before_transaction = cover_enable;
585
      coverage_settings_check(covergroup_settings_changed_flag, "c_idle_before_transaction");
586
   endfunction
587
 
588
   function automatic void set_enable_c_continuous_read( // public
589
      bit     cover_enable
590
   );
591
      // enable or disable c_continuous_read cover group
592
 
593
      enable_c_continuous_read = cover_enable;
594
      coverage_settings_check(covergroup_settings_changed_flag, "c_continuous_read");
595
   endfunction
596
 
597
   function automatic void set_enable_c_continuous_write( // public
598
      bit     cover_enable
599
   );
600
      // enable or disable c_continuous_write cover group
601
 
602
      enable_c_continuous_write = cover_enable;
603
      coverage_settings_check(covergroup_settings_changed_flag, "c_continuous_write");
604
   endfunction
605
 
606
   function automatic void set_enable_c_continuous_readdatavalid( // public
607
      bit     cover_enable
608
   );
609
      // enable or disable c_continuous_readdatavalid cover group
610
 
611
      enable_c_continuous_readdatavalid = cover_enable;
612
      coverage_settings_check(covergroup_settings_changed_flag, "c_continuous_readdatavalid");
613
   endfunction
614
 
615
   function automatic void set_enable_c_continuous_waitrequest( // public
616
      bit     cover_enable
617
   );
618
      // enable or disable c_continuous_waitrequest cover group
619
 
620
      enable_c_continuous_waitrequest = cover_enable;
621
      coverage_settings_check(covergroup_settings_changed_flag, "c_continuous_waitrequest");
622
   endfunction
623
 
624
   function automatic void set_enable_c_waitrequest_in_write_burst( // public
625
      bit     cover_enable
626
   );
627
      // enable or disable c_waitrequest_in_write_burst cover group
628
 
629
      enable_c_waitrequest_in_write_burst = cover_enable;
630
      coverage_settings_check(covergroup_settings_changed_flag, "c_waitrequest_in_write_burst");
631
   endfunction
632
 
633
   function automatic void set_enable_c_readresponse( // public
634
      bit     cover_enable
635
   );
636
      // enable or disable c_readresponse cover group
637
 
638
      // enable_c_readresponse = cover_enable;
639
      // coverage_settings_check(covergroup_settings_changed_flag, "c_readresponse");
640
 
641
      $sformat(message, "%m: This coverage is no longer supported. Please use c_read_response cover group");
642
      print(VERBOSITY_WARNING, message);
643
   endfunction
644
 
645
   function automatic void set_enable_c_writeresponse( // public
646
      bit     cover_enable
647
   );
648
      // enable or disable c_writeresponse cover group
649
 
650
      // enable_c_writeresponse = cover_enable;
651
      // coverage_settings_check(covergroup_settings_changed_flag, "c_writeresponse");
652
 
653
      $sformat(message, "%m: This coverage is no longer supported. Please use c_write_response cover group");
654
      print(VERBOSITY_WARNING, message);
655
   endfunction
656
 
657
   function automatic void set_enable_c_write_with_and_without_writeresponserequest( // public
658
      bit     cover_enable
659
   );
660
      // This API is no longer supported.
661
 
662
   endfunction
663
 
664
   function automatic void set_enable_c_write_after_reset( // public
665
      bit     cover_enable
666
   );
667
      // enable or disable c_write_after_reset cover group
668
 
669
      enable_c_write_after_reset = cover_enable;
670
      coverage_settings_check(covergroup_settings_changed_flag, "c_write_after_reset");
671
   endfunction
672
 
673
   function automatic void set_enable_c_read_after_reset( // public
674
      bit     cover_enable
675
   );
676
      // enable or disable c_read_after_reset cover group
677
 
678
      enable_c_read_after_reset = cover_enable;
679
      coverage_settings_check(covergroup_settings_changed_flag, "c_read_after_reset");
680
   endfunction
681
 
682
   function automatic void coverage_settings_check(
683
      bit cover_flag,
684
      string cover_name
685
   );
686
      string message;
687
      if (cover_flag) begin
688
         $sformat(message, "%m: - Changing %s covergroup settings during run-time will not be reflected",
689
                  cover_name);
690
         print(VERBOSITY_WARNING, message);
691
      end
692
   endfunction
693
 
694
   function automatic void set_enable_c_write_response( // public
695
      bit     cover_enable
696
   );
697
      // enable or disable c_write_response cover group
698
 
699
      enable_c_write_response = cover_enable;
700
      coverage_settings_check(covergroup_settings_changed_flag, "c_write_response");
701
   endfunction
702
 
703
   function automatic void set_enable_c_read_response( // public
704
      bit     cover_enable
705
   );
706
      // enable or disable c_read_response cover group
707
 
708
      enable_c_read_response = cover_enable;
709
      coverage_settings_check(covergroup_settings_changed_flag, "c_read_response");
710
   endfunction
711
 
712
   function automatic void set_enable_c_write_response_transition( // public
713
      bit     cover_enable
714
   );
715
      // enable or disable c_write_response_transition cover group
716
 
717
      enable_c_write_response_transition = cover_enable;
718
      coverage_settings_check(covergroup_settings_changed_flag, "c_write_response_transition");
719
   endfunction
720
 
721
   function automatic void set_enable_c_read_response_transition( // public
722
      bit     cover_enable
723
   );
724
      // enable or disable c_read_response_transition cover group
725
 
726
      enable_c_read_response_transition = cover_enable;
727
      coverage_settings_check(covergroup_settings_changed_flag, "c_read_response_transition");
728
   endfunction
729
 
730
   //--------------------------------------------------------------------------
731
   // =head1 Assertion Checkers and Coverage Monitors
732
   // The assertion checkers in this module are only executable on simulators
733
   // supporting the SystemVerilog Assertion (SVA) language.
734
   // Mentor Modelsim AE and SE do not support this.
735
   // Simulators that are supported include: Synopsys VCS and Mentor questasim.
736
   // The assertion checking logic in this module must be explicitly enabled
737
   // so that designs using this module can still be compiled on Modelsim without
738
   // changes. To disable assertions define the following macro in the testbench
739
   // or on the command line with: +define+DISABLE_ALTERA_AVALON_SIM_SVA.
740
   // =cut
741
   //--------------------------------------------------------------------------
742
 
743
   //counter to capture previous cycle waitrequest value
744
   always @(posedge clk)
745
   begin
746
      if (!reset) begin
747
         past_waitrequest = waitrequest;
748
      end
749
   end
750
 
751
   // Counter for general coverage counters
752
   always @(posedge clk) begin
753
      if (!USE_CLKEN || clken) begin
754
         if (idle_in_write_burst_start_flag) begin
755
            if (waitrequest) begin
756
               idle_in_write_burst_with_waitrequest = 1;
757
            end
758
         end
759
 
760
         // ignore the waitrequest effect while reset
761
         if ((read || write) &&
762
             reset_flag[1] == 0)
763
            reset_flag[0] = 0;
764
         if (($fell(read) || $fell(write) || readdatavalid ||
765
             $fell(begintransfer) || $fell(beginbursttransfer) ||
766
             ((read || write) && $fell(waitrequest))) &&
767
             reset_flag[0] == 0) begin
768
            reset_flag[1] = 1;
769
            reset_flag[0] = 1;
770
         end
771
 
772
         // Counter for read latency and readdatavalid_id
773
         if (!readdatavalid) begin
774
            read_latency_counter = 0;
775
         end
776
         if (read && !waitrequest && !readdatavalid) begin
777
            if (((!$fell(waitrequest) && !waitrequested_command_while_clken) || $rose(read)) ||
778
                read_command_while_clken || reset_flag[1] == 0) begin
779
               read_latency_start_flag[read_id] = 1;
780
               temp_read_latency_counter[read_id] = 0;
781
            end else begin
782
               if (read_id != 0) begin
783
                  read_latency_start_flag[read_id-1] = 1;
784
                  temp_read_latency_counter[read_id-1] = 0;
785
               end else begin
786
                  read_latency_start_flag[MAX_ID] = 1;
787
                  temp_read_latency_counter[MAX_ID] = 0;
788
               end
789
            end
790
         end
791
         if (!read && readdatavalid) begin
792
               read_latency_counter =
793
                  temp_read_latency_counter[readdatavalid_id];
794
            if (read_burst_counter[readdatavalid_id] == 1 ||
795
                read_burst_counter[readdatavalid_id] == 0) begin
796
               temp_read_latency_counter[readdatavalid_id] = 0;
797
               read_latency_start_flag[readdatavalid_id] = 0;
798
               // increase the id, restart the id from zero to reduce memory usage
799
               if (readdatavalid_id < (MAX_ID))
800
                  readdatavalid_id++;
801
               else
802
                  readdatavalid_id = 0;
803
            end
804
         end
805
         if (read && readdatavalid) begin
806
            read_latency_counter =
807
               temp_read_latency_counter[readdatavalid_id];
808
            if (!waitrequest) begin
809
               if (((!$fell(waitrequest) && !waitrequested_command_while_clken) || $rose(read)) ||
810
                   read_command_while_clken || reset_flag[1] == 0) begin
811
                  read_latency_start_flag[read_id] = 1;
812
                  temp_read_latency_counter[read_id] = 0;
813
               end else begin
814
                  if (read_id != 0) begin
815
                     read_latency_start_flag[read_id-1] = 1;
816
                     temp_read_latency_counter[read_id-1] = 0;
817
                  end else begin
818
                     read_latency_start_flag[MAX_ID] = 1;
819
                     temp_read_latency_counter[MAX_ID] = 0;
820
                  end
821
               end
822
            end
823
            if (read_burst_counter[readdatavalid_id] == 1 ||
824
                read_burst_counter[readdatavalid_id] == 0) begin
825
               temp_read_latency_counter[readdatavalid_id] = 0;
826
               read_latency_start_flag[readdatavalid_id] = 0;
827
               if (readdatavalid_id < (MAX_ID))
828
                  readdatavalid_id++;
829
               else
830
                  readdatavalid_id = 0;
831
            end
832
         end
833
 
834
         // new burst write transaction started
835
         if (((write && (!waitrequest || $rose(waitrequest)) &&
836
             ((!$fell(waitrequest) && !waitrequested_command_while_clken) ||
837
             reset_flag[1] == 0)) || write_command_while_clken || ($rose(write))) &&
838
             write_burst_counter == 0) begin
839
            if (burstcount > 0)
840
               write_burst_counter = burstcount;
841
            idle_write_flag = 1;
842
            idle_in_write_burst_start_flag = 1;
843
            idle_before_burst_transaction_sampled = 1;
844
         end
845
 
846
         if (write && (write_burst_counter == 1)) begin
847
            idle_in_write_burst_start_flag = 0;
848
            idle_in_write_burst_with_waitrequest_sampled = 1;
849
         end
850
 
851
         // decrease the write_burst_counter while write asserted
852
         if (write && !waitrequest && write_burst_counter > 0) begin
853
            write_burst_counter--;
854
         end
855
 
856
         // new read transaction asserted
857
         if (((read && (!waitrequest || $rose(waitrequest)) &&
858
               ((!$fell(waitrequest) && !waitrequested_command_while_clken) ||
859
               reset_flag[1] == 0)) || read_command_while_clken || $rose(read) ||
860
              (read_transaction_flag && waitrequest &&
861
               read_without_waitrequest_flag && read))) begin
862
            read_transaction_flag = 1;
863
            idle_before_burst_transaction_sampled = 1;
864
            if (continuous_read >= 2)
865
               continuous_read++;
866
            if (continuous_read_start_flag) begin
867
               if (continuous_read == 0)
868
                  continuous_read = 2;
869
            end
870
            continuous_read_start_flag = 1;
871
            continuous_read_sampled = 0;
872
         end else begin
873
            read_transaction_flag = 0;
874
            if (read) begin
875
               continuous_read_start_flag = 1;
876
               continuous_read_sampled = 0;
877
            end else begin
878
               continuous_read_start_flag = 0;
879
               continuous_read_sampled = 1;
880
            end
881
         end
882
 
883
         // new read transaction without previous read response(readdatavalid) returned at same cycle
884
         if (((read && (!waitrequest || $rose(waitrequest)) &&
885
            ((!$fell(waitrequest) && !waitrequested_command_while_clken) ||
886
            reset_flag[1] == 0)) || read_command_while_clken || $rose(read) ||
887
            (read_transaction_flag && waitrequest &&
888
            read_without_waitrequest_flag && read)) &&
889
            !readdatavalid) begin
890
            if (burstcount > 0) begin
891
               read_burst_counter[read_id] = burstcount;
892
               temp_read_burst_counter = burstcount;
893
            end
894
 
895
            if (!waitrequest)
896
               read_without_waitrequest_flag = 1;
897
            else
898
               read_without_waitrequest_flag = 0;
899
            idle_write_flag = 0;
900
            idle_read_flag[read_id] = 1;
901
            pending_read_counter++;
902
            if (read_id < (MAX_ID))
903
               read_id++;
904
            else
905
               read_id = 0;
906
         end
907
 
908
         // previous read response(readdatavalid) returned while no new read transaction asserted
909
         if ((readdatavalid ||
910
            (fix_latency_queued_counter != 0 &&
911
            fix_latency_queued_counter == AV_FIX_READ_LATENCY &&
912
            !USE_READ_DATA_VALID)) &&
913
            (!read_transaction_flag || !read) && pending_read_counter > 0) begin
914
            if ((readdatavalid_id == 0) && (read_burst_counter[MAX_ID] == 0)) begin
915
               if (read_burst_counter[readdatavalid_id] > 0) begin
916
                  if (read_burst_counter[readdatavalid_id] == 1) begin
917
                     pending_read_counter--;
918
                  end
919
                  read_burst_counter[readdatavalid_id]--;
920
               end
921
            end else if (read_id >= ((readdatavalid_id == 0)?MAX_ID-1:readdatavalid_id-1)) begin
922
               for (int i=0; i<=MAX_ID; i++) begin
923
                  if (read_burst_counter[i] > 0) begin
924
                     if (read_burst_counter[i] == 1) begin
925
                        pending_read_counter--;
926
                     end
927
                     read_burst_counter[i]--;
928
                     i=MAX_ID+1;
929
                  end
930
               end
931
            end else begin
932
               for (int i=((readdatavalid_id == 0)?MAX_ID-1:readdatavalid_id-1); i<=MAX_ID; i++) begin
933
                  if (read_burst_counter[i] > 0) begin
934
                     if (read_burst_counter[i] == 1) begin
935
                        pending_read_counter--;
936
                     end
937
                     read_burst_counter[i]--;
938
                     i=MAX_ID+1;
939
                  end
940
               end
941
            end
942
         end
943
 
944
         // new read transaction with previous read response(readdatavalid) returned at same cycle
945
         if (((read && (!waitrequest || $rose(waitrequest)) &&
946
            ((!$fell(waitrequest) && !waitrequested_command_while_clken) ||
947
            reset_flag[1] == 0)) || read_command_while_clken || $rose(read) ||
948
            (read_transaction_flag && waitrequest &&
949
            read_without_waitrequest_flag && read)) &&
950
            (readdatavalid ||
951
            (fix_latency_queued_counter != 0 &&
952
            fix_latency_queued_counter == AV_FIX_READ_LATENCY &&
953
            !USE_READ_DATA_VALID)) &&
954
            pending_read_counter > 0) begin
955
            if ((readdatavalid_id == 0) && (read_burst_counter[MAX_ID] == 0)) begin
956
               if (read_burst_counter[readdatavalid_id] > 0) begin
957
                  if (read_burst_counter[readdatavalid_id] == 1) begin
958
                     pending_read_counter--;
959
                  end
960
                  read_burst_counter[readdatavalid_id]--;
961
               end
962
            end else if (read_id >= ((readdatavalid_id == 0)?MAX_ID-1:readdatavalid_id-1)) begin
963
               for (int i=0; i<=MAX_ID; i++) begin
964
                  if (read_burst_counter[i] > 0) begin
965
                     if (read_burst_counter[i] == 1) begin
966
                        pending_read_counter--;
967
                     end
968
                     read_burst_counter[i]--;
969
                     i=MAX_ID+1;
970
                  end
971
               end
972
            end else begin
973
               for (int i=((readdatavalid_id == 0)?MAX_ID-1:readdatavalid_id-1); i<=MAX_ID; i++) begin
974
                  if (read_burst_counter[i] > 0) begin
975
                     if (read_burst_counter[i] == 1) begin
976
                        pending_read_counter--;
977
                     end
978
                     read_burst_counter[i]--;
979
                     i=MAX_ID+1;
980
                  end
981
               end
982
            end
983
            if (burstcount > 0) begin
984
               read_burst_counter[read_id] = burstcount;
985
               temp_read_burst_counter = burstcount;
986
            end
987
            if (!waitrequest)
988
               read_without_waitrequest_flag = 1;
989
            else
990
               read_without_waitrequest_flag = 0;
991
            idle_write_flag = 0;
992
            idle_read_flag[read_id] = 1;
993
            pending_read_counter++;
994
            if (read_id < (MAX_ID))
995
               read_id++;
996
            else
997
               read_id = 0;
998
         end
999
 
1000
         // counter for read latency
1001
         if (pending_read_counter > 0) begin
1002
            if (!USE_READ_DATA_VALID) begin
1003
               fix_read_latency_counter++;
1004
               if (fix_read_latency_counter >
1005
                   AV_FIX_READ_LATENCY)
1006
                  fix_read_latency_counter = 0;
1007
            end else begin
1008
               for (int i=0; i<=MAX_ID; i++) begin
1009
                  if (i != read_id) begin
1010
                     if (read_latency_start_flag[i]) begin
1011
                        temp_read_latency_counter[i]++;
1012
                     end
1013
                  end
1014
               end
1015
            end
1016
         end
1017
 
1018
         // counter for idle_in_write_burst
1019
         if (idle_in_write_burst_flag) begin
1020
            idle_write_flag = 0;
1021
            idle_in_write_burst_flag = 0;
1022
         end
1023
         if (!write && idle_write_flag &&
1024
             write_burst_counter < burstcount &&
1025
             write_burst_counter != 0)
1026
            idle_in_write_burst_flag = 1;
1027
 
1028
         // counter for idle_in_read_response
1029
         if (idle_in_read_response == 1)
1030
            idle_in_read_response = 0;
1031
         if (!readdatavalid && !waitrequest &&
1032
             idle_read_flag[readdatavalid_id] &&
1033
             read_burst_counter[readdatavalid_id] <=
1034
             temp_read_burst_counter) begin
1035
            temp_idle_in_read_response[readdatavalid_id]++;
1036
            idle_in_read_response =
1037
               temp_idle_in_read_response[readdatavalid_id];
1038
         end
1039
 
1040
         // counter for waitrequested command
1041
         if (read && waitrequest)
1042
            temp_waitrequested_read_counter++;
1043
         if (!read || !waitrequest) begin
1044
            waitrequested_read_counter =
1045
               temp_waitrequested_read_counter;
1046
            temp_waitrequested_read_counter = 0;
1047
         end
1048
         if (write && waitrequest) begin
1049
            temp_waitrequested_write_counter++;
1050
         end
1051
         if (!write || !waitrequest) begin
1052
            waitrequested_write_counter =
1053
               temp_waitrequested_write_counter;
1054
            temp_waitrequested_write_counter = 0;
1055
         end
1056
 
1057
         // fix latency counter
1058
         if (read && !waitrequest) begin
1059
            fix_latency_queued.push_front(0);
1060
         end
1061
 
1062
         if (fix_latency_queued.size() > 0) begin
1063
            foreach(fix_latency_queued[size]) begin
1064
               fix_latency_queued[size]++;
1065
               if (fix_latency_queued[size] > AV_FIX_READ_LATENCY) begin
1066
                  void'(fix_latency_queued.pop_back());
1067
               end
1068
            end
1069
            fix_latency_queued_counter <= fix_latency_queued[$];
1070
         end
1071
         waitrequested_command_while_clken = 0;
1072
         write_command_while_clken = 0;
1073
         read_command_while_clken = 0;
1074
      end else begin
1075
         if (($rose(waitrequest) && read) || ($rose(read))) begin
1076
            read_command_while_clken = 1;
1077
         end
1078
         if (($rose(waitrequest) && write) || $rose(write)) begin
1079
            write_command_while_clken = 1;
1080
         end
1081
 
1082
         if ($fell(waitrequest) && (read || write)) begin
1083
            waitrequested_command_while_clken = 1;
1084
         end
1085
      end
1086
   end
1087
 
1088
   // counter for waitrequest before command asserted
1089
   always @(posedge clk) begin
1090
      if (!reset) begin
1091
         if (!USE_CLKEN || clken) begin
1092
            if (waitrequest && !write && !read) begin
1093
               waitrequest_before_command = 1;
1094
               waitrequested_before_transaction = 1;
1095
            end else begin
1096
               if (read || write) begin
1097
                  waitrequested_before_transaction = 0;
1098
               end
1099
            end
1100
 
1101
            if (waitrequest && (read || write)) begin
1102
               if (write_burst_counter == 0)
1103
                  burst_waitrequested_command = 1;
1104
            end
1105
 
1106
            if (waitrequest_before_command) begin
1107
               if (write && waitrequest) begin
1108
                  waitrequest_before_waitrequested_write = 1;
1109
               end else if (read && waitrequest) begin
1110
                  waitrequest_before_waitrequested_read = 1;
1111
               end
1112
 
1113
               if(!waitrequest) begin
1114
                  if (!waitrequest_before_waitrequested_write && !waitrequest_before_waitrequested_read) begin
1115
                     waitrequest_without_command = 1;
1116
                  end else begin
1117
                     waitrequest_without_command = 0;
1118
                  end
1119
                  waitrequest_before_command = 0;
1120
               end
1121
            end else begin
1122
               waitrequest_before_waitrequested_write = 0;
1123
               waitrequest_before_waitrequested_read = 0;
1124
            end
1125
 
1126
            if (!waitrequest) begin
1127
               waitrequest_before_command = 0;
1128
            end
1129
 
1130
            if (!read && ! write && !waitrequest) begin
1131
               if (write_burst_counter == 0) begin
1132
                  idle_before_burst_transaction = 1;
1133
                  idle_before_burst_transaction_sampled = 0;
1134
               end
1135
            end
1136
 
1137
            if (waitrequested_before_transaction) begin
1138
               if (idle_before_burst_transaction) begin
1139
                  idle_before_burst_transaction_with_waitrequest = 1;
1140
                  idle_before_burst_transaction_with_waitrequest_sampled = 0;
1141
               end
1142
            end else begin
1143
               if ((burst_waitrequested_command) && (idle_before_burst_transaction)) begin
1144
                  idle_before_burst_transaction_with_waitrequest = 1;
1145
               end
1146
               if (write_burst_counter == 0) begin
1147
                  idle_before_burst_transaction_with_waitrequest_sampled = 1;
1148
               end else begin
1149
                  idle_before_burst_transaction_with_waitrequest_sampled = 0;
1150
               end
1151
            end
1152
         end
1153
      end
1154
   end
1155
 
1156
   // Counter for continuous write, readdatavalid
1157
   always@(posedge clk) begin
1158
      if (!reset) begin
1159
         if (!USE_CLKEN || clken) begin
1160
            if ((write && (!waitrequest))) begin
1161
               if (continuous_write >= 2)
1162
                  continuous_write++;
1163
               if (continuous_write_start_flag) begin
1164
                  if (continuous_write == 0)
1165
                     continuous_write = 2;
1166
               end else begin
1167
                  continuous_write_start_flag = 1;
1168
               end
1169
 
1170
               continuous_write_start_flag = 1;
1171
               continuous_write_sampled = 0;
1172
            end else begin
1173
               if (write) begin
1174
                  continuous_write_sampled = 0;
1175
               end else begin
1176
                  continuous_write_sampled = 1;
1177
                  continuous_write_start_flag = 0;
1178
               end
1179
            end
1180
 
1181
            if (readdatavalid) begin
1182
               if (continuous_readdatavalid >= 2)
1183
                  continuous_readdatavalid++;
1184
               if(continuous_readdatavalid_start_flag == 1) begin
1185
                  if (continuous_readdatavalid == 0)
1186
                     continuous_readdatavalid = 2;
1187
               end
1188
               continuous_readdatavalid_sampled = 0;
1189
               continuous_readdatavalid_start_flag = 1;
1190
            end else begin
1191
               continuous_readdatavalid_start_flag = 0;
1192
               continuous_readdatavalid_sampled = 1;
1193
            end
1194
 
1195
            if (waitrequest) begin
1196
               if (continuous_waitrequest >= 1)
1197
                     continuous_waitrequest++;
1198
               if(continuous_waitrequest_start_flag == 1) begin
1199
                  if (continuous_waitrequest == 0) begin
1200
                     continuous_waitrequest = 2;
1201
                  end
1202
               end
1203
               continuous_waitrequest_sampled = 0;
1204
               continuous_waitrequest_start_flag = 1;
1205
            end else begin
1206
               continuous_waitrequest_start_flag = 0;
1207
               continuous_waitrequest_sampled = 1;
1208
            end
1209
         end
1210
      end
1211
   end
1212
 
1213
   // Counter for generating legal byteenable
1214
   initial begin
1215
      legal_byteenable[(AV_NUMSYMBOLS*2)-1] = 0;
1216
      check_byteenable = byteenable_1_bit;
1217
      for (int i=0; i
1218
         legal_byteenable[i] = check_byteenable;
1219
         check_byteenable = check_byteenable << 1;
1220
         byteenable_counter = i;
1221
      end
1222
      if (AV_NUMSYMBOLS > 1) begin
1223
         check_byteenable = byteenable_2_bit;
1224
         for (int i=0; i
1225
            byteenable_counter++;
1226
            legal_byteenable[byteenable_counter] = check_byteenable;
1227
            check_byteenable = check_byteenable << 2;
1228
         end
1229
      end
1230
      if (AV_NUMSYMBOLS > 2) begin
1231
         check_byteenable = byteenable_4_bit;
1232
         for (int i=0; i
1233
            byteenable_counter++;
1234
            legal_byteenable[byteenable_counter] = check_byteenable;
1235
            check_byteenable = check_byteenable << 4;
1236
         end
1237
      end
1238
      if (AV_NUMSYMBOLS > 4) begin
1239
         check_byteenable = byteenable_8_bit;
1240
         for (int i=0; i
1241
            byteenable_counter++;
1242
            legal_byteenable[byteenable_counter] = check_byteenable;
1243
            check_byteenable = check_byteenable << 8;
1244
         end
1245
      end
1246
      if (AV_NUMSYMBOLS > 8) begin
1247
         check_byteenable = byteenable_16_bit;
1248
         for (int i=0; i
1249
            byteenable_counter++;
1250
            legal_byteenable[byteenable_counter] = check_byteenable;
1251
            check_byteenable = check_byteenable << 16;
1252
         end
1253
      end
1254
      if (AV_NUMSYMBOLS > 16) begin
1255
         check_byteenable = byteenable_32_bit;
1256
         for (int i=0; i
1257
            byteenable_counter++;
1258
            legal_byteenable[byteenable_counter] = check_byteenable;
1259
            check_byteenable = check_byteenable << 32;
1260
         end
1261
      end
1262
      if (AV_NUMSYMBOLS > 32) begin
1263
         check_byteenable = byteenable_64_bit;
1264
         for (int i=0; i
1265
            byteenable_counter++;
1266
            legal_byteenable[byteenable_counter] = check_byteenable;
1267
            check_byteenable = check_byteenable << 64;
1268
         end
1269
      end
1270
      if (AV_NUMSYMBOLS > 64) begin
1271
         byteenable_counter++;
1272
         legal_byteenable[byteenable_counter] = byteenable_128_bit;
1273
      end
1274
   end
1275
 
1276
   // Counter for back to back transfers
1277
   always @(posedge clk) begin
1278
      if (!USE_CLKEN || clken) begin
1279
         if ((!read && !write) || waitrequest) begin
1280
            b2b_transfer[3] = 1;
1281
            b2b_transfer[2] = 0;
1282
         end else begin
1283
            if (read && !waitrequest) begin
1284
               if (!b2b_transfer[3] && !b2b_transfer[2])
1285
                  b2b_transfer[1] = b2b_transfer[0];
1286
               if (b2b_transfer[3]) begin
1287
                  b2b_transfer[3] = 0;
1288
                  b2b_transfer[2] = 1;
1289
                  b2b_transfer[1] = 0;
1290
               end else begin
1291
                  b2b_transfer[0] = 0;
1292
                  if (b2b_transfer[2])
1293
                     b2b_transfer[2] = 0;
1294
               end
1295
            end
1296
            if (write && !waitrequest) begin
1297
               if (!b2b_transfer[3] && !b2b_transfer[2])
1298
                  b2b_transfer[1] = b2b_transfer[0];
1299
               if (b2b_transfer[3]) begin
1300
                  b2b_transfer[3] = 0;
1301
                  b2b_transfer[2] = 1;
1302
                  b2b_transfer[1] = 1;
1303
               end else begin
1304
                  b2b_transfer[0] = 1;
1305
                  if (b2b_transfer[2])
1306
                     b2b_transfer[2] = 0;
1307
               end
1308
            end
1309
         end
1310
      end
1311
   end
1312
 
1313
   // Counter for write response transition
1314
   always @(posedge clk) begin
1315
      if (!USE_CLKEN || clken) begin
1316
         if (writeresponsevalid) begin
1317
            write_response_transition[3:2] = write_response_transition[1:0];
1318
            write_response_transition[1:0] = write_response;
1319
         end
1320
      end
1321
   end
1322
 
1323
   // Counter for read response transition
1324
   always @(posedge clk) begin
1325
      if (!USE_CLKEN || clken) begin
1326
         if ((USE_READ_DATA_VALID && readdatavalid) ||
1327
               (!USE_READ_DATA_VALID && fix_latency_queued_counter == AV_FIX_READ_LATENCY && fix_latency_queued_counter != 0)) begin
1328
            read_response_transition[3:2] = read_response_transition[1:0];
1329
            read_response_transition[1:0] = read_response;
1330
         end
1331
      end
1332
   end
1333
   // Counter for reset
1334
   always @(posedge clk) begin
1335
      if (reset) begin
1336
         fix_latency_queued = {};
1337
         idle_write_flag = 0;
1338
         idle_read_flag = 0;
1339
         read_latency_start_flag = 0;
1340
         read_burst_counter = 0;
1341
         temp_read_burst_counter = 0;
1342
         temp_idle_in_read_response = 0;
1343
         temp_read_latency_counter = 0;
1344
         fix_latency_queued_counter = 0;
1345
         read_transaction_flag = 0;
1346
         read_without_waitrequest_flag = 0;
1347
         idle_in_write_burst_flag = 0;
1348
         write_burst_counter = 0;
1349
         pending_read_counter = 0;
1350
         fix_read_latency_counter = 0;
1351
         idle_in_read_response = 0;
1352
         temp_waitrequested_read_counter = 0;
1353
         waitrequested_read_counter = 0;
1354
         temp_waitrequested_write_counter = 0;
1355
         waitrequested_write_counter = 0;
1356
         byteenable_counter = 0;
1357
         read_latency_counter = 0;
1358
         read_id = 0;
1359
         readdatavalid_id = 0;
1360
         b2b_transfer = 4'b1111;
1361
         check_byteenable = 0;
1362
         reset_flag[1] = 0;
1363
         reset_flag[0] = 1;
1364
         write_after_reset = 1;
1365
         read_after_reset = 1;
1366
         read_reset_transaction = 1;
1367
         write_reset_transaction = 1;
1368
         waitrequest_before_waitrequested_read = 0;
1369
         waitrequest_before_waitrequested_write = 0;
1370
         waitrequest_before_command = 0;
1371
         waitrequest_without_command = 0;
1372
         past_waitrequest = 0;
1373
         idle_before_burst_transaction = 0;
1374
         idle_before_burst_transaction_sampled = 0;
1375
         continuous_read_sampled = 0;
1376
         continuous_read_start_flag = 0;
1377
         continuous_read = 0;
1378
         continuous_write_sampled = 0;
1379
         continuous_write_start_flag = 0;
1380
         continuous_write = 0;
1381
         continuous_readdatavalid_sampled = 0;
1382
         continuous_readdatavalid_start_flag = 0;
1383
         continuous_readdatavalid = 0;
1384
         continuous_waitrequest_sampled = 0;
1385
         continuous_waitrequest_start_flag = 0;
1386
         continuous_waitrequest = 0;
1387
         idle_in_write_burst_with_waitrequest = 0;
1388
         idle_in_write_burst_with_waitrequest_sampled = 0;
1389
         idle_in_write_burst_start_flag = 0;
1390
         idle_before_burst_transaction_with_waitrequest = 0;
1391
         idle_before_burst_transaction_with_waitrequest_sampled = 0;
1392
         waitrequested_before_transaction = 0;
1393
         burst_waitrequested_command = 0;
1394
         write_command_while_clken = 0;
1395
         read_command_while_clken = 0;
1396
         waitrequested_command_while_clken = 0;
1397
      end
1398
   end
1399
 
1400
   // Flag for initial coverage settings
1401
   initial begin
1402
      #1 covergroup_settings_changed_flag = 1;
1403
   end
1404
 
1405
 
1406
   `ifdef DISABLE_ALTERA_AVALON_SIM_SVA
1407
   // SVA coverage code is disabled when this macro is defined
1408
 
1409
   `else
1410
   //--------------------------------------------------------------------------
1411
   // COVERAGE CODE BEGIN
1412
   //--------------------------------------------------------------------------
1413
 
1414
   //---------------------------------------------------------------------------
1415
   // =head2 Master Coverages
1416
   // The following are the cover group code focus on Master component coverage
1417
   //-------------------------------------------------------------------------------
1418
 
1419
   //-------------------------------------------------------------------------------
1420
   // =head3 c_read_byteenable
1421
   // This cover group covers the different byteenable during read transfers.
1422
   // This cover group does not support byteenable value larger than
1423
   // 1073741824.
1424
   //-------------------------------------------------------------------------------
1425
 
1426
   covergroup cg_read_byteenable(logic [63:0] byteenable_max);
1427
      cp_byteenable: coverpoint byteenable
1428
      {
1429
         bins cg_read_byteenable_cp_byteenable [] = {[0:4],
1430
                                                     8,
1431
                                                     12,
1432
                                                     15,
1433
                                                     16,
1434
                                                     32,
1435
                                                     48,
1436
                                                     64,
1437
                                                     128,
1438
                                                     192,
1439
                                                     255,
1440
                                                     256,
1441
                                                     512,
1442
                                                     768,
1443
                                                     1024,
1444
                                                     2048,
1445
                                                     3072,
1446
                                                     3840,
1447
                                                     4096,
1448
                                                     8192,
1449
                                                     12288,
1450
                                                     16384,
1451
                                                     32768,
1452
                                                     49152,
1453
                                                     65280,
1454
                                                     65535,
1455
                                                     65536,
1456
                                                     131072,
1457
                                                     196608,
1458
                                                     262144,
1459
                                                     524288,
1460
                                                     786432,
1461
                                                     1048576,
1462
                                                     2097152,
1463
                                                     3145728,
1464
                                                     4194304,
1465
                                                     8388608,
1466
                                                     12582912,
1467
                                                     16711680,
1468
                                                     16777216,
1469
                                                     33554432,
1470
                                                     50331648,
1471
                                                     67108864,
1472
                                                     134217728,
1473
                                                     201326592,
1474
                                                     268435456,
1475
                                                     536870912,
1476
                                                     805306368,
1477
                                                     1073741824};
1478
 
1479
         ignore_bins cg_read_byteenable_cp_byteenable_ignore = {[byteenable_max+1:$]};
1480
      }
1481
      option.per_instance = 1;
1482
   endgroup
1483
 
1484
   cg_read_byteenable c_read_byteenable;
1485
 
1486
   initial begin
1487
      #1 if (enable_c_read_byteenable && USE_BYTE_ENABLE && USE_READ) begin
1488
         if (AV_NUMSYMBOLS >= 32)
1489
            c_read_byteenable = new(1073741825);
1490
         else
1491
            c_read_byteenable = new((2**AV_NUMSYMBOLS)-1);
1492
      end
1493
   end
1494
 
1495
   always @(posedge clk && !reset) begin
1496
      if (enable_c_read_byteenable && USE_BYTE_ENABLE && USE_READ) begin
1497
         if (read && !waitrequest && clken) begin
1498
            c_read_byteenable.sample();
1499
         end
1500
      end
1501
   end
1502
 
1503
   // -------------------------------------------------------------------------------
1504
   // =head3 c_write_byteenable
1505
   // This cover group covers the different byteenable during write transfers.
1506
   // This cover group does not support byteenable value larger than
1507
   // 1073741824.
1508
   // -------------------------------------------------------------------------------
1509
 
1510
   covergroup cg_write_byteenable(logic [31:0] byteenable_max);
1511
      cp_byteenable: coverpoint byteenable
1512
      {
1513
         bins cg_write_byteenable_cp_byteenable [] = {[0:4],
1514
                                                     8,
1515
                                                     12,
1516
                                                     15,
1517
                                                     16,
1518
                                                     32,
1519
                                                     48,
1520
                                                     64,
1521
                                                     128,
1522
                                                     192,
1523
                                                     255,
1524
                                                     256,
1525
                                                     512,
1526
                                                     768,
1527
                                                     1024,
1528
                                                     2048,
1529
                                                     3072,
1530
                                                     3840,
1531
                                                     4096,
1532
                                                     8192,
1533
                                                     12288,
1534
                                                     16384,
1535
                                                     32768,
1536
                                                     49152,
1537
                                                     65280,
1538
                                                     65535,
1539
                                                     65536,
1540
                                                     131072,
1541
                                                     196608,
1542
                                                     262144,
1543
                                                     524288,
1544
                                                     786432,
1545
                                                     1048576,
1546
                                                     2097152,
1547
                                                     3145728,
1548
                                                     4194304,
1549
                                                     8388608,
1550
                                                     12582912,
1551
                                                     16711680,
1552
                                                     16777216,
1553
                                                     33554432,
1554
                                                     50331648,
1555
                                                     67108864,
1556
                                                     134217728,
1557
                                                     201326592,
1558
                                                     268435456,
1559
                                                     536870912,
1560
                                                     805306368,
1561
                                                     1073741824};
1562
         ignore_bins cg_write_byteenable_cp_byteenable_ignore = {[byteenable_max+1:$]};
1563
      }
1564
      option.per_instance = 1;
1565
   endgroup
1566
 
1567
   cg_write_byteenable c_write_byteenable;
1568
 
1569
   initial begin
1570
      #1 if (enable_c_write_byteenable && USE_BYTE_ENABLE && USE_WRITE) begin
1571
         if (AV_NUMSYMBOLS >= 32)
1572
            c_write_byteenable = new(1073741825);
1573
         else
1574
            c_write_byteenable = new((2**AV_NUMSYMBOLS)-1);
1575
      end
1576
   end
1577
 
1578
   always @(posedge clk && !reset) begin
1579
      if (enable_c_write_byteenable && USE_BYTE_ENABLE && USE_WRITE) begin
1580
         if (write && !waitrequest && clken) begin
1581
            c_write_byteenable.sample();
1582
         end
1583
      end
1584
   end
1585
 
1586
   //-------------------------------------------------------------------------------
1587
   // =head3 c_read_burstcount
1588
   // This cover group covers the different sizes of burstcount during read
1589
   // burst transfers
1590
   //-------------------------------------------------------------------------------
1591
 
1592
   covergroup cg_read_burstcount;
1593
      cp_burstcount: coverpoint burstcount
1594
      {
1595
         bins cg_read_burstcount_cp_burstcount_low = {1};
1596
         bins cg_read_burstcount_cp_burstcount_mid =
1597
            {[(AV_MAX_BURST < 3? 1:2):
1598
              (AV_MAX_BURST < 3? 1:AV_MAX_BURST-1)]};
1599
         bins cg_read_burstcount_cp_burstcount_high =
1600
            {(AV_MAX_BURST < 2? 1:AV_MAX_BURST)};
1601
      }
1602
      option.per_instance = 1;
1603
   endgroup
1604
 
1605
   cg_read_burstcount c_read_burstcount;
1606
 
1607
   initial begin
1608
      #1 if (enable_c_read_burstcount && USE_BURSTCOUNT && USE_READ) begin
1609
         c_read_burstcount = new();
1610
      end
1611
   end
1612
 
1613
   always @(posedge clk && !reset) begin
1614
      if (enable_c_read_burstcount && USE_BURSTCOUNT && USE_READ) begin
1615
         if (read && !waitrequest && clken) begin
1616
            c_read_burstcount.sample();
1617
            #1;
1618
         end
1619
      end
1620
   end
1621
 
1622
   //-------------------------------------------------------------------------------
1623
   // =head3 c_write_burstcount
1624
   // This cover group covers the different sizes of burstcount during write
1625
   // burst transfers
1626
   //-------------------------------------------------------------------------------
1627
 
1628
   covergroup cg_write_burstcount;
1629
      cp_burstcount: coverpoint burstcount
1630
      {
1631
         bins cg_write_burstcount_cp_burstcount_low = {1};
1632
         bins cg_write_burstcount_cp_burstcount_mid =
1633
            {[(AV_MAX_BURST < 3? 1:2):
1634
              (AV_MAX_BURST < 3? 1:AV_MAX_BURST-1)]};
1635
         bins cg_write_burstcount_cp_burstcount_high =
1636
            {(AV_MAX_BURST < 2? 1:AV_MAX_BURST)};
1637
      }
1638
      option.per_instance = 1;
1639
   endgroup
1640
 
1641
   cg_write_burstcount c_write_burstcount;
1642
 
1643
   initial begin
1644
      #1 if (enable_c_write_burstcount && USE_BURSTCOUNT && USE_WRITE) begin
1645
         c_write_burstcount = new();
1646
      end
1647
   end
1648
 
1649
   always @(posedge clk && !reset) begin
1650
      if (enable_c_write_burstcount && USE_BURSTCOUNT && USE_WRITE) begin
1651
         if (write && write_burst_counter == 0 && clken) begin
1652
            c_write_burstcount.sample();
1653
            #1;
1654
         end
1655
      end
1656
   end
1657
 
1658
   //-------------------------------------------------------------------------------
1659
   // =head3 c_pending_read
1660
   // This cover group covers the different number of pending read transfers
1661
   //-------------------------------------------------------------------------------
1662
 
1663
   covergroup cg_pending_read;
1664
      cp_pending_read_count: coverpoint pending_read_counter
1665
      {
1666
         bins cg_pending_read_cp_pending_read_count[] =
1667
           {[1:(AV_MAX_PENDING_READS < 2? 1:AV_MAX_PENDING_READS)]};
1668
      }
1669
      option.per_instance = 1;
1670
   endgroup
1671
 
1672
   cg_pending_read c_pending_read;
1673
 
1674
   initial begin
1675
      #1 if (enable_c_pending_read && USE_READ && USE_READ_DATA_VALID && AV_MAX_PENDING_READS > 0) begin
1676
         c_pending_read = new();
1677
      end
1678
   end
1679
 
1680
   always @(posedge clk && !reset) begin
1681
      if (enable_c_pending_read && USE_READ && USE_READ_DATA_VALID && AV_MAX_PENDING_READS > 0) begin
1682
         if (read_transaction_flag && clken) begin
1683
            c_pending_read.sample();
1684
            #1;
1685
         end
1686
      end
1687
   end
1688
 
1689
   //-------------------------------------------------------------------------------
1690
   // =head3 c_read
1691
   // This cover group covers read transfers
1692
   //-------------------------------------------------------------------------------
1693
 
1694
   covergroup cg_read;
1695
      cp_read: coverpoint read
1696
      {
1697
         bins cg_read_cp_read = {1};
1698
         option.comment = "This cover group covers read transfers";
1699
      }
1700
      option.per_instance = 1;
1701
      option.comment = "This cover group covers how many read transfers happen";
1702
   endgroup
1703
 
1704
   cg_read c_read;
1705
 
1706
   initial begin
1707
      #1 if (enable_c_read && USE_READ) begin
1708
         c_read = new();
1709
      end
1710
   end
1711
 
1712
   always @(posedge clk && !reset) begin
1713
      if (enable_c_read && USE_READ && clken) begin
1714
         if (read && !waitrequest) begin
1715
            c_read.sample();
1716
            #1;
1717
         end
1718
      end
1719
   end
1720
 
1721
   //-------------------------------------------------------------------------------
1722
   // =head3 c_write
1723
   // This cover group covers write transfers
1724
   //-------------------------------------------------------------------------------
1725
 
1726
   covergroup cg_write;
1727
      cp_write: coverpoint write
1728
      {
1729
         bins cg_write_cp_write = {1};
1730
      }
1731
      option.per_instance = 1;
1732
   endgroup
1733
 
1734
   cg_write c_write;
1735
 
1736
   initial begin
1737
      #1 if (enable_c_write && USE_WRITE) begin
1738
         c_write = new();
1739
      end
1740
   end
1741
 
1742
   always @(posedge clk && !reset) begin
1743
      if (enable_c_write && USE_WRITE && clken) begin
1744
         if (write && write_burst_counter == 0) begin
1745
            c_write.sample();
1746
            #1;
1747
         end
1748
      end
1749
   end
1750
 
1751
   //-------------------------------------------------------------------------------
1752
   // =head3 c_b2b_read_read
1753
   // This cover group covers back to back read to read transfers
1754
   //-------------------------------------------------------------------------------
1755
 
1756
   covergroup cg_b2b_read_read;
1757
      cp_b2b_read_read: coverpoint b2b_transfer
1758
      {
1759
         bins cp_b2b_read_read_cp_b2b_read_read = {4'b0000};
1760
      }
1761
      option.per_instance = 1;
1762
   endgroup
1763
 
1764
   cg_b2b_read_read c_b2b_read_read;
1765
 
1766
   initial begin
1767
      #1 if (enable_c_b2b_read_read && USE_READ) begin
1768
         c_b2b_read_read = new();
1769
      end
1770
   end
1771
 
1772
   always @(posedge clk && !reset) begin
1773
      if (enable_c_b2b_read_read && USE_READ && clken) begin
1774
         c_b2b_read_read.sample();
1775
         #1;
1776
      end
1777
   end
1778
 
1779
   //-------------------------------------------------------------------------------
1780
   // =head3 c_b2b_read_write
1781
   // This cover group covers back to back read to write transfers
1782
   //-------------------------------------------------------------------------------
1783
 
1784
   covergroup cg_b2b_read_write;
1785
      cp_b2b_read_write: coverpoint b2b_transfer
1786
      {
1787
         bins cg_b2b_read_write_cp_b2b_read_write = {4'b0001};
1788
      }
1789
      option.per_instance = 1;
1790
   endgroup
1791
 
1792
   cg_b2b_read_write c_b2b_read_write;
1793
 
1794
   initial begin
1795
      #1 if (enable_c_b2b_read_write && USE_READ && USE_WRITE) begin
1796
         c_b2b_read_write = new();
1797
      end
1798
   end
1799
 
1800
   always @(posedge clk && !reset) begin
1801
      if (enable_c_b2b_read_write && USE_READ && USE_WRITE && clken) begin
1802
         c_b2b_read_write.sample();
1803
         #1;
1804
      end
1805
   end
1806
 
1807
   //-------------------------------------------------------------------------------
1808
   // =head3 c_b2b_write_write
1809
   // This cover group covers back to back write to write transfers
1810
   //-------------------------------------------------------------------------------
1811
 
1812
   covergroup cg_b2b_write_write;
1813
      cp_b2b_write_write: coverpoint b2b_transfer
1814
      {
1815
         bins cg_b2b_write_write_cp_b2b_write_write = {4'b0011};
1816
      }
1817
      option.per_instance = 1;
1818
   endgroup
1819
 
1820
   cg_b2b_write_write c_b2b_write_write;
1821
 
1822
   initial begin
1823
      #1 if (enable_c_b2b_write_write && USE_WRITE) begin
1824
         c_b2b_write_write = new();
1825
      end
1826
   end
1827
 
1828
   always @(posedge clk && !reset) begin
1829
      if (enable_c_b2b_write_write && USE_WRITE && clken) begin
1830
         c_b2b_write_write.sample();
1831
         #1;
1832
      end
1833
   end
1834
 
1835
   //-------------------------------------------------------------------------------
1836
   // =head3 c_b2b_write_read
1837
   // This cover group covers back to back write to read transfers
1838
   //-------------------------------------------------------------------------------
1839
 
1840
   covergroup cg_b2b_write_read;
1841
      cp_b2b_write_read: coverpoint b2b_transfer
1842
      {
1843
         bins cg_b2b_write_read_cp_b2b_write_read = {4'b0010};
1844
      }
1845
      option.per_instance = 1;
1846
   endgroup
1847
 
1848
   cg_b2b_write_read c_b2b_write_read;
1849
 
1850
   initial begin
1851
      #1 if (enable_c_b2b_write_read && USE_READ && USE_WRITE) begin
1852
         c_b2b_write_read = new();
1853
      end
1854
   end
1855
 
1856
   always @(posedge clk && !reset) begin
1857
      if (enable_c_b2b_write_read && USE_READ && USE_WRITE && clken) begin
1858
         c_b2b_write_read.sample();
1859
         #1;
1860
      end
1861
   end
1862
 
1863
   //-------------------------------------------------------------------------------
1864
   // =head3 c_idle_in_write_burst
1865
   // This cover group covers idle cycles during write burst transfers
1866
   //-------------------------------------------------------------------------------
1867
 
1868
   covergroup cg_idle_in_write_burst;
1869
      cp_idle_in_write_burst: coverpoint idle_in_write_burst_flag
1870
      {
1871
         bins cg_idle_in_write_burst_cp_idle_in_write_burst_count = {1};
1872
      }
1873
      option.per_instance = 1;
1874
   endgroup
1875
 
1876
   cg_idle_in_write_burst c_idle_in_write_burst;
1877
 
1878
   initial begin
1879
      #1 if (enable_c_idle_in_write_burst && USE_BURSTCOUNT && USE_WRITE &&
1880
             AV_MAX_BURST > 1) begin
1881
         c_idle_in_write_burst = new();
1882
      end
1883
   end
1884
 
1885
   always @(posedge clk && !reset) begin
1886
      if (enable_c_idle_in_write_burst && USE_BURSTCOUNT && USE_WRITE &&
1887
          AV_MAX_BURST > 1 && clken) begin
1888
         c_idle_in_write_burst.sample();
1889
         #1;
1890
      end
1891
   end
1892
 
1893
   //-------------------------------------------------------------------------------
1894
   // =head3 c_idle_before_transaction
1895
   // This cover group covers different cycle numbers of idle before read/write
1896
   // transaction.
1897
   //-------------------------------------------------------------------------------
1898
 
1899
   covergroup cg_idle_before_transaction;
1900
      cp_idle_before_transaction: coverpoint idle_before_burst_transaction
1901
      {
1902
         bins cg_idle_before_transaction_cp_idle_before_transaction = {1};
1903
      }
1904
      option.per_instance = 1;
1905
   endgroup
1906
 
1907
   cg_idle_before_transaction c_idle_before_transaction;
1908
 
1909
   initial begin
1910
      #1 if (enable_c_idle_before_transaction) begin
1911
         c_idle_before_transaction = new();
1912
      end
1913
   end
1914
 
1915
   always @(posedge clk && !reset) begin
1916
      if (idle_before_burst_transaction_sampled == 1 && clken) begin
1917
         if (enable_c_idle_before_transaction) begin
1918
            c_idle_before_transaction.sample();
1919
            #1;
1920
         end
1921
         idle_before_burst_transaction = 0;
1922
      end
1923
   end
1924
 
1925
   //-------------------------------------------------------------------------------
1926
   // =head3 c_continuous_read
1927
   // This cover group covers the different cycle numbers of continuous read
1928
   // asserted from 2 until AV_MAX_CONTINUOUS_READ. For the continuous read cycles
1929
   // more than AV_MAX_CONTINUOUS_READ will go to another bin.
1930
   //-------------------------------------------------------------------------------
1931
 
1932
   covergroup cg_continuous_read;
1933
      cp_continuous_read: coverpoint continuous_read
1934
      {
1935
         bins cg_continuous_read_cp_continuous_read [] =
1936
            {[2:(AV_MAX_CONTINUOUS_READ < 2) ? 2:AV_MAX_CONTINUOUS_READ]};
1937
         bins cg_continuous_read_cp_continuous_read_high =
1938
            {[AV_MAX_CONTINUOUS_READ+1:$]};
1939
      }
1940
      option.per_instance = 1;
1941
   endgroup
1942
 
1943
   cg_continuous_read c_continuous_read;
1944
 
1945
   initial begin
1946
      #1 if (enable_c_continuous_read && USE_READ) begin
1947
         c_continuous_read = new();
1948
      end
1949
   end
1950
 
1951
   always @(posedge clk && !reset) begin
1952
      if (enable_c_continuous_read && USE_READ && clken) begin
1953
         if (continuous_read_sampled == 1) begin
1954
            c_continuous_read.sample();
1955
            continuous_read = 0;
1956
            #1;
1957
         end
1958
      end
1959
   end
1960
 
1961
   //-------------------------------------------------------------------------------
1962
   // =head3 c_continuous_write
1963
   // This cover group covers the different cycle numbers of continuous write
1964
   // asserted from 2 until AV_MAX_CONTINUOUS_WRITE. For the continuous write cycles
1965
   // more than AV_MAX_CONTINUOUS_WRITE will go to another bin.
1966
   //-------------------------------------------------------------------------------
1967
 
1968
   covergroup cg_continuous_write;
1969
      cp_continuous_write: coverpoint continuous_write
1970
      {
1971
         bins cg_continuous_write_cp_continuous_write [] =
1972
            {[2:(AV_MAX_CONTINUOUS_WRITE) < 2 ? 2:AV_MAX_CONTINUOUS_WRITE]};
1973
         bins cg_continuous_write_cp_continuous_write_high =
1974
            {[AV_MAX_CONTINUOUS_WRITE+1:$]};
1975
      }
1976
      option.per_instance = 1;
1977
   endgroup
1978
 
1979
   cg_continuous_write c_continuous_write;
1980
 
1981
   initial begin
1982
      #1 if (enable_c_continuous_write && USE_WRITE) begin
1983
         c_continuous_write = new();
1984
      end
1985
   end
1986
 
1987
   always @(posedge clk && !reset) begin
1988
      if (enable_c_continuous_write && USE_WRITE && clken) begin
1989
         if (continuous_write_sampled == 1) begin
1990
            c_continuous_write.sample();
1991
            continuous_write = 0;
1992
            #1;
1993
         end
1994
      end
1995
   end
1996
 
1997
   //-------------------------------------------------------------------------------
1998
   // =head3 c_write_after_reset
1999
   // This cover group covers write transaction right after reset
2000
   //-------------------------------------------------------------------------------
2001
 
2002
   covergroup cg_write_after_reset;
2003
      cp_write_after_reset: coverpoint write_after_reset
2004
      {
2005
         bins cg_write_after_reset_cp_write_after_reset = {1};
2006
      }
2007
      option.per_instance = 1;
2008
   endgroup
2009
 
2010
   cg_write_after_reset c_write_after_reset;
2011
 
2012
   initial begin
2013
      #1 if (enable_c_write_after_reset && USE_WRITE) begin
2014
         c_write_after_reset = new();
2015
      end
2016
   end
2017
 
2018
   always @(posedge clk) begin
2019
      if (enable_c_write_after_reset && USE_WRITE && !reset && clken) begin
2020
         if (write) begin
2021
            c_write_after_reset.sample();
2022
            #1;
2023
         end
2024
         if (write_reset_transaction == 0) begin
2025
            write_after_reset = 0;
2026
         end
2027
         write_reset_transaction = 0;
2028
      end
2029
   end
2030
 
2031
   //-------------------------------------------------------------------------------
2032
   // =head3 c_read_after_reset
2033
   // This cover group covers read transaction right after reset
2034
   // =cut
2035
   //-------------------------------------------------------------------------------
2036
 
2037
   covergroup cg_read_after_reset;
2038
      cp_read_after_reset: coverpoint read_after_reset
2039
      {
2040
         bins cg_read_after_reset_cp_read_after_reset = {1};
2041
      }
2042
      option.per_instance = 1;
2043
   endgroup
2044
 
2045
   cg_read_after_reset c_read_after_reset;
2046
 
2047
   initial begin
2048
      #1 if (enable_c_read_after_reset && USE_READ) begin
2049
         c_read_after_reset = new();
2050
      end
2051
   end
2052
 
2053
   always @(posedge clk) begin
2054
      if (enable_c_read_after_reset && USE_READ && !reset && clken) begin
2055
         if (read) begin
2056
            c_read_after_reset.sample();
2057
            #1;
2058
         end
2059
         if (read_reset_transaction == 0) begin
2060
            read_after_reset = 0;
2061
         end
2062
         read_reset_transaction = 0;
2063
      end
2064
   end
2065
 
2066
   //-------------------------------------------------------------------------------
2067
   // =head2 Slave Coverages
2068
   // The following are the cover group code focus on Slave component coverage
2069
   //-------------------------------------------------------------------------------
2070
 
2071
   //-------------------------------------------------------------------------------
2072
   // =head3 c_idle_in_read_response
2073
   // This cover group covers idle cycles during read response
2074
   //-------------------------------------------------------------------------------
2075
 
2076
   covergroup cg_idle_in_read_response;
2077
      cp_idle_in_read_response: coverpoint idle_in_read_response
2078
      {
2079
         bins cg_idle_in_read_response_cp_idle_in_read_response_count = {1};
2080
      }
2081
      option.per_instance = 1;
2082
   endgroup
2083
 
2084
   cg_idle_in_read_response c_idle_in_read_response;
2085
 
2086
   initial begin
2087
      #1 if (enable_c_idle_in_read_response && USE_BURSTCOUNT && USE_READ &&
2088
             USE_READ_DATA_VALID) begin
2089
         c_idle_in_read_response = new();
2090
      end
2091
   end
2092
 
2093
   always @(posedge clk && !reset) begin
2094
      if (enable_c_idle_in_read_response && USE_BURSTCOUNT && USE_READ &&
2095
          USE_READ_DATA_VALID && clken) begin
2096
         c_idle_in_read_response.sample();
2097
         #1;
2098
      end
2099
   end
2100
 
2101
   //-------------------------------------------------------------------------------
2102
   // =head3 c_read_latency
2103
   // This cover group covers different read latency cycles
2104
   //-------------------------------------------------------------------------------
2105
 
2106
   covergroup cg_read_latency;
2107
      cp_read_latency: coverpoint read_latency_counter
2108
      {
2109
         bins cg_read_latency_cp_read_latency_count_low = {1};
2110
         bins cg_read_latency_cp_read_latency_count_high =
2111
            {[(AV_MAX_READ_LATENCY < 2? 1:2):
2112
              (AV_MAX_READ_LATENCY < 2? 1:AV_MAX_READ_LATENCY)]};
2113
      }
2114
      option.per_instance = 1;
2115
   endgroup
2116
 
2117
   cg_read_latency c_read_latency;
2118
 
2119
   initial begin
2120
      #1 if (enable_c_read_latency && USE_READ && USE_READ_DATA_VALID &&
2121
             AV_MAX_READ_LATENCY > 0) begin
2122
         c_read_latency = new();
2123
      end
2124
   end
2125
 
2126
   always @(posedge clk && !reset) begin
2127
      if (enable_c_read_latency && USE_READ && USE_READ_DATA_VALID &&
2128
          AV_MAX_READ_LATENCY > 0 && clken) begin
2129
         c_read_latency.sample();
2130
         #1;
2131
      end
2132
   end
2133
 
2134
   //-------------------------------------------------------------------------------
2135
   // =head3 c_waitrequested_read
2136
   // This cover group covers different waitrequested read cycles
2137
   //-------------------------------------------------------------------------------
2138
 
2139
   covergroup cg_waitrequested_read;
2140
      cp_waitrequested_read_cycle: coverpoint waitrequested_read_counter
2141
      {
2142
         bins cg_waitrequested_read_cp_waitrequested_read_cycle_low = {1};
2143
         bins cg_waitrequested_read_cp_waitrequested_read_cycle_high =
2144
            {[(AV_MAX_WAITREQUESTED_READ < 2? 1:2):
2145
              (AV_MAX_WAITREQUESTED_READ < 2? 1:AV_MAX_WAITREQUESTED_READ)]};
2146
      }
2147
      option.per_instance = 1;
2148
   endgroup
2149
 
2150
   cg_waitrequested_read c_waitrequested_read;
2151
 
2152
   initial begin
2153
      #1 if (enable_c_waitrequested_read && USE_WAIT_REQUEST && USE_READ &&
2154
             AV_MAX_WAITREQUESTED_READ > 0) begin
2155
         c_waitrequested_read = new();
2156
      end
2157
   end
2158
 
2159
   always @(posedge clk && !reset) begin
2160
      if (enable_c_waitrequested_read && USE_WAIT_REQUEST && USE_READ &&
2161
          AV_MAX_WAITREQUESTED_READ > 0 && clken) begin
2162
         if (temp_waitrequested_read_counter == 0) begin
2163
            c_waitrequested_read.sample();
2164
            #1;
2165
         end
2166
      end
2167
   end
2168
 
2169
   //-------------------------------------------------------------------------------
2170
   // =head3 c_waitrequested_write
2171
   // This cover group covers different waitrequested write cycles
2172
   //-------------------------------------------------------------------------------
2173
 
2174
   covergroup cg_waitrequested_write;
2175
      cp_waitrequested_write_cycle: coverpoint waitrequested_write_counter
2176
      {
2177
         bins cg_waitrequested_write_cp_waitrequested_write_cycle_low = {1};
2178
         bins cg_waitrequested_write_cp_waitrequested_write_cycle_high =
2179
            {[(AV_MAX_WAITREQUESTED_WRITE < 2? 1:2):
2180
              (AV_MAX_WAITREQUESTED_WRITE < 2? 1:AV_MAX_WAITREQUESTED_WRITE)]};
2181
      }
2182
      option.per_instance = 1;
2183
   endgroup
2184
 
2185
   cg_waitrequested_write c_waitrequested_write;
2186
 
2187
   initial begin
2188
      #1 if (enable_c_waitrequested_write && USE_WAIT_REQUEST && USE_WRITE &&
2189
             AV_MAX_WAITREQUESTED_WRITE > 0) begin
2190
         c_waitrequested_write = new();
2191
      end
2192
   end
2193
 
2194
   always @(posedge clk && !reset) begin
2195
      if (enable_c_waitrequested_write && USE_WAIT_REQUEST && USE_WRITE &&
2196
          AV_MAX_WAITREQUESTED_WRITE > 0 && clken) begin
2197
         if (temp_waitrequested_write_counter == 0) begin
2198
            c_waitrequested_write.sample();
2199
            #1;
2200
         end
2201
      end
2202
   end
2203
 
2204
   //-------------------------------------------------------------------------------
2205
   // =head3 c_continuous_waitrequest_from_idle_to_write
2206
   // This cover group covers waitrequest is asserted before waitrequested write.
2207
   //-------------------------------------------------------------------------------
2208
 
2209
   covergroup cg_continuous_waitrequest_from_idle_to_write;
2210
      cp_continuous_waitrequest_from_idle_to_write: coverpoint waitrequest_before_waitrequested_write
2211
      {
2212
         bins cg_continuous_waitrequest_from_idle_to_write_cp_continuous_waitrequest_from_idle_to_write = {1};
2213
      }
2214
      option.per_instance = 1;
2215
   endgroup
2216
 
2217
   cg_continuous_waitrequest_from_idle_to_write c_continuous_waitrequest_from_idle_to_write;
2218
 
2219
   initial begin
2220
      #1 if (enable_c_continuous_waitrequest_from_idle_to_write && USE_WAIT_REQUEST && USE_WRITE &&
2221
             AV_MAX_WAITREQUESTED_WRITE > 0) begin
2222
         c_continuous_waitrequest_from_idle_to_write = new();
2223
      end
2224
   end
2225
 
2226
   always @(posedge clk && !reset) begin
2227
      if (!waitrequest && clken) begin
2228
         if (enable_c_continuous_waitrequest_from_idle_to_write && USE_WAIT_REQUEST && USE_WRITE &&
2229
             AV_MAX_WAITREQUESTED_WRITE > 0) begin
2230
            c_continuous_waitrequest_from_idle_to_write.sample();
2231
            #1;
2232
         end
2233
         waitrequest_before_waitrequested_write = 0;
2234
      end
2235
   end
2236
 
2237
   //-------------------------------------------------------------------------------
2238
   // =head3 c_continuous_waitrequest_from_idle_to_read
2239
   // This cover group covers waitrequest is asserted before waitrequested read.
2240
   //-------------------------------------------------------------------------------
2241
 
2242
   covergroup cg_continuous_waitrequest_from_idle_to_read;
2243
      cp_continuous_waitrequest_from_idle_to_read: coverpoint waitrequest_before_waitrequested_read
2244
      {
2245
         bins cg_continuous_waitrequest_from_idle_to_read_cp_continuous_waitrequest_from_idle_to_read = {1};
2246
      }
2247
      option.per_instance = 1;
2248
   endgroup
2249
 
2250
   cg_continuous_waitrequest_from_idle_to_read c_continuous_waitrequest_from_idle_to_read;
2251
 
2252
   initial begin
2253
      #1 if (enable_c_continuous_waitrequest_from_idle_to_read && USE_WAIT_REQUEST && USE_READ &&
2254
             AV_MAX_WAITREQUESTED_READ > 0) begin
2255
         c_continuous_waitrequest_from_idle_to_read = new();
2256
      end
2257
   end
2258
 
2259
   always @(posedge clk && !reset) begin
2260
      if (!waitrequest && clken) begin
2261
         if (enable_c_continuous_waitrequest_from_idle_to_read && USE_WAIT_REQUEST && USE_READ &&
2262
             AV_MAX_WAITREQUESTED_READ > 0) begin
2263
            c_continuous_waitrequest_from_idle_to_read.sample();
2264
            #1;
2265
         end
2266
         waitrequest_before_waitrequested_read = 0;
2267
      end
2268
   end
2269
 
2270
   //-------------------------------------------------------------------------------
2271
   // =head3 c_waitrequest_without_command
2272
   // This cover group covers no command has been asserted for the period
2273
   // waitrequest is asserted and then deasserted.
2274
   //-------------------------------------------------------------------------------
2275
 
2276
   covergroup cg_waitrequest_without_command;
2277
      cp_waitrequest_without_command: coverpoint waitrequest_without_command
2278
      {
2279
         bins cg_waitrequest_without_command_cp_waitrequest_without_command = {1};
2280
      }
2281
      option.per_instance = 1;
2282
   endgroup
2283
 
2284
   cg_waitrequest_without_command c_waitrequest_without_command;
2285
 
2286
   initial begin
2287
      #1 if (enable_c_waitrequest_without_command && USE_WAIT_REQUEST) begin
2288
         c_waitrequest_without_command = new();
2289
      end
2290
   end
2291
 
2292
   always @(posedge clk && !reset) begin
2293
      if (enable_c_waitrequest_without_command && USE_WAIT_REQUEST && clken) begin
2294
         c_waitrequest_without_command.sample();
2295
         waitrequest_without_command = 0;
2296
         #1;
2297
      end
2298
   end
2299
 
2300
   //-------------------------------------------------------------------------------
2301
   // =head3 c_continuous_readdatavalid
2302
   // This cover group covers the different cycle numbers of continuous
2303
   // readdatavalid asserted from 2 until AV_MAX_CONTINUOUS_READDATAVALID. For the
2304
   // continuous readdatavalid cycles more than AV_MAX_CONTINUOUS_READDATAVALID will
2305
   // go to another bin.
2306
   //-------------------------------------------------------------------------------
2307
 
2308
   covergroup cg_continuous_readdatavalid;
2309
      cp_continuous_readdatavalid: coverpoint continuous_readdatavalid
2310
      {
2311
         bins cg_continuous_readdatavalid_cp_continuous_readdatavalid [] =
2312
            {[2:(AV_MAX_CONTINUOUS_READDATAVALID < 2) ? 2:AV_MAX_CONTINUOUS_READDATAVALID]};
2313
         bins cg_continuous_readdatavalid_cp_continuous_readdatavalid_high =
2314
            {[AV_MAX_CONTINUOUS_READDATAVALID+1:$]};
2315
      }
2316
      option.per_instance = 1;
2317
   endgroup
2318
 
2319
   cg_continuous_readdatavalid c_continuous_readdatavalid;
2320
 
2321
   initial begin
2322
      #1 if (enable_c_continuous_readdatavalid && USE_READ_DATA_VALID) begin
2323
         c_continuous_readdatavalid = new();
2324
      end
2325
   end
2326
 
2327
   always @(posedge clk && !reset) begin
2328
      if (enable_c_continuous_readdatavalid && USE_READ_DATA_VALID && clken) begin
2329
         if (continuous_readdatavalid_sampled == 1) begin
2330
            c_continuous_readdatavalid.sample();
2331
            continuous_readdatavalid = 0;
2332
            #1;
2333
         end
2334
      end
2335
   end
2336
 
2337
   //-------------------------------------------------------------------------------
2338
   // =head3 c_continuous_waitrequest
2339
   // This cover group covers the different cycle numbers of continuous waitrequest
2340
   // asserted from 2 until AV_MAX_CONTINUOUS_WAITREQUEST. For the continuous
2341
   // waitrequest cycles more than AV_MAX_CONTINUOUS_WAITREQUEST will go to another
2342
   // bin.
2343
   //-------------------------------------------------------------------------------
2344
 
2345
   covergroup cg_continuous_waitrequest;
2346
      cp_continuous_waitrequest: coverpoint continuous_waitrequest
2347
      {
2348
         bins cg_continuous_waitrequest_cp_continuous_waitrequest [] =
2349
            {[2:(AV_MAX_CONTINUOUS_WAITREQUEST < 2) ? 2:AV_MAX_CONTINUOUS_WAITREQUEST]};
2350
         bins cg_continuous_waitrequest_cp_continuous_waitrequest_high =
2351
            {[AV_MAX_CONTINUOUS_WAITREQUEST+1:$]};
2352
      }
2353
      option.per_instance = 1;
2354
   endgroup
2355
 
2356
   cg_continuous_waitrequest c_continuous_waitrequest;
2357
 
2358
   initial begin
2359
      #1 if (enable_c_continuous_waitrequest && USE_WAIT_REQUEST) begin
2360
         c_continuous_waitrequest = new();
2361
      end
2362
   end
2363
 
2364
   always @(posedge clk && !reset) begin
2365
      if (enable_c_continuous_waitrequest && USE_WAIT_REQUEST && clken) begin
2366
         if (continuous_waitrequest_sampled == 1) begin
2367
            c_continuous_waitrequest.sample();
2368
            continuous_waitrequest = 0;
2369
            #1;
2370
         end
2371
      end
2372
   end
2373
 
2374
   //-------------------------------------------------------------------------------
2375
   // =head3 c_waitrequest_in_write_burst
2376
   // This cover group covers the different number of cycles for idle cycle during
2377
   // write burst transaction with different number of cycles for waitrequest.
2378
   //-------------------------------------------------------------------------------
2379
 
2380
   covergroup cg_waitrequest_in_write_burst;
2381
      cp_waitrequest_in_write_burst: coverpoint idle_in_write_burst_with_waitrequest
2382
      {
2383
         bins cg_waitrequest_in_write_burst_cp_waitrequest_in_write_burst = {1};
2384
      }
2385
      option.per_instance = 1;
2386
   endgroup
2387
 
2388
   cg_waitrequest_in_write_burst c_waitrequest_in_write_burst;
2389
 
2390
   initial begin
2391
      #1 if (enable_c_waitrequest_in_write_burst && USE_WAIT_REQUEST && USE_WRITE && USE_BURSTCOUNT && (AV_BURSTCOUNT_W > 1)) begin
2392
         c_waitrequest_in_write_burst = new();
2393
      end
2394
   end
2395
 
2396
   always @(posedge clk && !reset) begin
2397
      if (enable_c_waitrequest_in_write_burst && USE_WAIT_REQUEST && USE_BURSTCOUNT && USE_WRITE && (AV_BURSTCOUNT_W > 1)) begin
2398
         if (idle_in_write_burst_with_waitrequest_sampled == 1 && clken) begin
2399
            c_waitrequest_in_write_burst.sample();
2400
            idle_in_write_burst_with_waitrequest = 0;
2401
            idle_in_write_burst_with_waitrequest_sampled = 0;
2402
            #1;
2403
         end
2404
      end
2405
   end
2406
 
2407
   //-------------------------------------------------------------------------------
2408
   // =head3 c_readresponse
2409
   // This cover group covers each bits of the valid readresponse which represent
2410
   // different status.
2411
   //-------------------------------------------------------------------------------
2412
 
2413
   // covergroup cg_readresponse;
2414
      // cp_readresponse: coverpoint readresponse_bit_num
2415
      // {
2416
         // bins cg_readresponse_cp_readresponse [] = {[0:(AV_READRESPONSE_W-1)]};
2417
      // }
2418
      // option.per_instance = 1;
2419
   // endgroup
2420
 
2421
   // cg_readresponse c_readresponse;
2422
 
2423
   // initial begin
2424
      // #1 if (enable_c_readresponse && USE_READRESPONSE && USE_READ) begin
2425
           // c_readresponse = new();
2426
      // end
2427
   // end
2428
 
2429
   // always @(posedge clk && !reset) begin
2430
      // if (enable_c_readresponse && USE_READRESPONSE && USE_READ && clken) begin
2431
         // if ((USE_READ_DATA_VALID && readdatavalid) || (!USE_READ_DATA_VALID)) begin
2432
            // for (int i=0; i
2433
               // if (readresponse[i] == 1)
2434
                  // readresponse_bit_num = i;
2435
               // else
2436
                  // readresponse_bit_num = AV_READRESPONSE_W;
2437
               // c_readresponse.sample();
2438
            // end
2439
         // end
2440
         // #1;
2441
      // end
2442
   // end
2443
 
2444
   //-------------------------------------------------------------------------------
2445
   // =head3 c_writeresponse
2446
   // This cover group covers each bits of the valid writeresponse which represent
2447
   // different status.
2448
   //-------------------------------------------------------------------------------
2449
 
2450
   // covergroup cg_writeresponse;
2451
      // cp_writeresponse : coverpoint writeresponse_bit_num
2452
      // {
2453
         // bins cg_writeresponse_cp_writeresponse [] = {[0:(AV_WRITERESPONSE_W-1)]};
2454
      // }
2455
      // option.per_instance = 1;
2456
   // endgroup
2457
 
2458
   // cg_writeresponse c_writeresponse;
2459
 
2460
   // initial begin
2461
      // #1 if (enable_c_writeresponse && USE_WRITERESPONSE && USE_WRITE) begin
2462
         // c_writeresponse = new();
2463
      // end
2464
   // end
2465
 
2466
   // always @(posedge clk && !reset) begin
2467
      // if (enable_c_writeresponse && USE_WRITERESPONSE && USE_WRITE  && clken) begin
2468
         // if (writeresponsevalid) begin
2469
            // for (int i=0; i
2470
               // if (writeresponse[i] == 1)
2471
                  // writeresponse_bit_num = i;
2472
               // else
2473
                  // writeresponse_bit_num = AV_WRITERESPONSE_W;
2474
               // c_writeresponse.sample();
2475
            // end
2476
         // end
2477
         // #1;
2478
      // end
2479
   // end
2480
 
2481
   //-------------------------------------------------------------------------------
2482
   // =head3 c_write_response
2483
   // This cover group covers the value of write response
2484
   //-------------------------------------------------------------------------------
2485
 
2486
   covergroup cg_write_response;
2487
      cp_write_response : coverpoint write_response
2488
      {
2489
         bins cg_write_response_cp_write_response [] = {AV_OKAY, AV_DECODE_ERROR, AV_SLAVE_ERROR};
2490
      }
2491
   endgroup
2492
 
2493
   cg_write_response c_write_response;
2494
 
2495
   initial begin
2496
      #1 if (enable_c_write_response && USE_WRITERESPONSE && USE_WRITE) begin
2497
         c_write_response = new();
2498
      end
2499
   end
2500
 
2501
   always @(posedge clk && !reset) begin
2502
      if (enable_c_write_response && USE_WRITERESPONSE && USE_WRITE  && clken) begin
2503
         if (writeresponsevalid) begin
2504
            if (!$cast(write_response, response))
2505
               begin
2506
                  $sformat(message, "%m: Response value is not valid when write response is valid");
2507
                  print(VERBOSITY_FAILURE, message);
2508
               end
2509
            c_write_response.sample();
2510
         end
2511
         #1;
2512
      end
2513
   end
2514
 
2515
   //-------------------------------------------------------------------------------
2516
   // =head3 c_read_response
2517
   // This cover group covers the value of read response
2518
   //-------------------------------------------------------------------------------
2519
 
2520
   covergroup cg_read_response;
2521
      cp_read_response : coverpoint read_response
2522
      {
2523
         bins cg_read_response_cp_read_response [] = {AV_OKAY, AV_DECODE_ERROR, AV_SLAVE_ERROR};
2524
      }
2525
   endgroup
2526
 
2527
   cg_read_response c_read_response;
2528
 
2529
   initial begin
2530
      #1 if (enable_c_read_response && USE_READRESPONSE && USE_READ) begin
2531
         c_read_response = new();
2532
      end
2533
   end
2534
 
2535
   always @(posedge clk && !reset) begin
2536
      if (enable_c_read_response && USE_READRESPONSE && USE_READ && clken) begin
2537
         if ((USE_READ_DATA_VALID && readdatavalid) ||
2538
               (!USE_READ_DATA_VALID && fix_latency_queued_counter == AV_FIX_READ_LATENCY && fix_latency_queued_counter != 0)) begin
2539
 
2540
            if (!$cast(read_response, response))
2541
               begin
2542
                  $sformat(message, "%m: Response value is not valid when read response is valid");
2543
                  print(VERBOSITY_FAILURE, message);
2544
               end
2545
            c_read_response.sample();
2546
         end
2547
         #1;
2548
      end
2549
   end
2550
 
2551
   //-------------------------------------------------------------------------------
2552
   // =head3 c_write_response_transition
2553
   // This cover group covers the value of write response
2554
   //-------------------------------------------------------------------------------
2555
 
2556
   covergroup cg_write_response_transition;
2557
      cp_write_response_transition : coverpoint write_response_transition
2558
      {
2559
         bins cg_write_response_transition_cp_write_response_transition_OKAY_TO_OKAY                  = {4'b0000};
2560
         bins cg_write_response_transition_cp_write_response_transition_OKAY_TO_SLAVE_ERROR           = {4'b0010};
2561
         bins cg_write_response_transition_cp_write_response_transition_OKAY_TO_DECODE_ERROR          = {4'b0011};
2562
         bins cg_write_response_transition_cp_write_response_transition_SLAVE_ERROR_TO_OKAY           = {4'b1000};
2563
         bins cg_write_response_transition_cp_write_response_transition_SLAVE_ERROR_TO_SLAVE_ERROR    = {4'b1010};
2564
         bins cg_write_response_transition_cp_write_response_transition_SLAVE_ERROR_TO_DECODE_ERROR   = {4'b1011};
2565
         bins cg_write_response_transition_cp_write_response_transition_DECODE_ERROR_TO_OKAY          = {4'b1100};
2566
         bins cg_write_response_transition_cp_write_response_transition_DECODE_ERROR_TO_SLAVE_ERROR   = {4'b1110};
2567
         bins cg_write_response_transition_cp_write_response_transition_DECODE_ERROR_TO_DECODE_ERROR  = {4'b1111};
2568
      }
2569
   endgroup
2570
 
2571
   cg_write_response_transition c_write_response_transition;
2572
 
2573
   initial begin
2574
      #1 if (enable_c_write_response_transition && USE_WRITERESPONSE && USE_WRITE) begin
2575
         c_write_response_transition = new();
2576
      end
2577
   end
2578
 
2579
   always @(posedge clk && !reset) begin
2580
      if (enable_c_write_response_transition && USE_WRITERESPONSE && USE_WRITE  && clken) begin
2581
         if (writeresponsevalid) begin
2582
            c_write_response_transition.sample();
2583
         end
2584
         #1;
2585
      end
2586
   end
2587
 
2588
   //-------------------------------------------------------------------------------
2589
   // =head3 c_read_response_transition
2590
   // This cover group covers the value of read response
2591
   //-------------------------------------------------------------------------------
2592
 
2593
   covergroup cg_read_response_transition;
2594
      cp_read_response_transition : coverpoint read_response_transition
2595
      {
2596
         bins cg_read_response_transition_cp_read_response_transition_OKAY_TO_OKAY                  = {4'b0000};
2597
         bins cg_read_response_transition_cp_read_response_transition_OKAY_TO_SLAVE_ERROR           = {4'b0010};
2598
         bins cg_read_response_transition_cp_read_response_transition_OKAY_TO_DECODE_ERROR          = {4'b0011};
2599
         bins cg_read_response_transition_cp_read_response_transition_SLAVE_ERROR_TO_OKAY           = {4'b1000};
2600
         bins cg_read_response_transition_cp_read_response_transition_SLAVE_ERROR_TO_SLAVE_ERROR    = {4'b1010};
2601
         bins cg_read_response_transition_cp_read_response_transition_SLAVE_ERROR_TO_DECODE_ERROR   = {4'b1011};
2602
         bins cg_read_response_transition_cp_read_response_transition_DECODE_ERROR_TO_OKAY          = {4'b1100};
2603
         bins cg_read_response_transition_cp_read_response_transition_DECODE_ERROR_TO_SLAVE_ERROR   = {4'b1110};
2604
         bins cg_read_response_transition_cp_read_response_transition_DECODE_ERROR_TO_DECODE_ERROR  = {4'b1111};
2605
      }
2606
   endgroup
2607
 
2608
   cg_read_response_transition c_read_response_transition;
2609
 
2610
   initial begin
2611
      #1 if (enable_c_read_response_transition && USE_READRESPONSE && USE_READ) begin
2612
         c_read_response_transition = new();
2613
      end
2614
   end
2615
 
2616
   always @(posedge clk && !reset) begin
2617
      if (enable_c_read_response_transition && USE_READRESPONSE && USE_READ  && clken) begin
2618
         if ((USE_READ_DATA_VALID && readdatavalid) ||
2619
               (!USE_READ_DATA_VALID && fix_latency_queued_counter == AV_FIX_READ_LATENCY && fix_latency_queued_counter != 0)) begin
2620
            c_read_response_transition.sample();
2621
         end
2622
         #1;
2623
      end
2624
   end
2625
 
2626
   //--------------------------------------------------------------------------
2627
   // COVERAGE CODE END
2628
   //--------------------------------------------------------------------------
2629
   `endif
2630
 
2631
   // synthesis translate_on
2632
 
2633
endmodule

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