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[/] [qaz_libs/] [trunk/] [avalon_lib/] [sim/] [tests/] [tb_ast_monitor/] [tb_ast_monitor.sv] - Blame information for rev 32

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1 32 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module tb_top();
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  // --------------------------------------------------------------------
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  // test bench clock & reset
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  wire clk_100mhz;
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  wire tb_clk = clk_100mhz;
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  wire tb_rst;
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  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
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  // --------------------------------------------------------------------
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  //
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  wire tb_rst_s;
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  wire clk    = tb_clk;
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  wire reset  = tb_rst_s;
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  sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
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  // --------------------------------------------------------------------
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  //
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  import tb_ast_monitor_pkg::*;
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  // --------------------------------------------------------------------
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  //
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  ast_if #(EW, CW, SW, NSW) src(.*);
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  ast_if #(EW, CW, SW, NSW) sink(.*);
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  // --------------------------------------------------------------------
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  //
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  // --------------------------------------------------------------------
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  // sim models
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  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
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  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
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  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
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  // --------------------------------------------------------------------
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  //
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  ast_monitor
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    #(
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      .ST_SYMBOL_W(ST_SYMBOL_W),
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      .ST_NUMSYMBOLS(ST_NUMSYMBOLS),
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      .USE_PACKET(USE_PACKET),
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      .ST_READY_LATENCY(ST_READY_LATENCY),
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      .USE_CHANNEL(USE_CHANNEL),
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      .USE_ERROR(USE_ERROR),
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      .USE_READY(USE_READY),
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      .USE_VALID(USE_VALID),
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      .USE_EMPTY(USE_EMPTY),
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      .ST_ERROR_W(ST_ERROR_W),
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      .ST_MAX_PACKET_SIZE(ST_MAX_PACKET_SIZE),
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      .ST_MAX_CHANNELS(ST_MAX_CHANNELS)
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    )
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    ast_monitor_i(.sink(src), .src(sink), .*);
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  // --------------------------------------------------------------------
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  //
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  ast_source
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    #(
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      .ST_SYMBOL_W(ST_SYMBOL_W),
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      .ST_NUMSYMBOLS(ST_NUMSYMBOLS),
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      .USE_PACKET(USE_PACKET),
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      .ST_READY_LATENCY(ST_READY_LATENCY),
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      .USE_CHANNEL(USE_CHANNEL),
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      .USE_ERROR(USE_ERROR),
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      .USE_READY(USE_READY),
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      .USE_VALID(USE_VALID),
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      .USE_EMPTY(USE_EMPTY),
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      .ST_ERROR_W(ST_ERROR_W),
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      .ST_MAX_CHANNELS(ST_MAX_CHANNELS)
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    )
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    ast_source_i(.*);
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  // --------------------------------------------------------------------
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  //
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  ast_sink
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    #(
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      .ST_SYMBOL_W(ST_SYMBOL_W),
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      .ST_NUMSYMBOLS(ST_NUMSYMBOLS),
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      .USE_PACKET(USE_PACKET),
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      .ST_READY_LATENCY(ST_READY_LATENCY),
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      .USE_CHANNEL(USE_CHANNEL),
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      .USE_ERROR(USE_ERROR),
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      .USE_READY(USE_READY),
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      .USE_VALID(USE_VALID),
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      .USE_EMPTY(USE_EMPTY),
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      .ST_ERROR_W(ST_ERROR_W),
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      .ST_MAX_CHANNELS(ST_MAX_CHANNELS)
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    )
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    ast_sink_i(.*);
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  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
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  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
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  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
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  // sim models
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  // --------------------------------------------------------------------
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  // --------------------------------------------------------------------
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  // test
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  the_test test( tb_clk, tb_rst );
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  initial
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    begin
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      test.run_the_test();
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      $display("^^^---------------------------------");
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      $display("^^^ %16.t | Testbench done.", $time);
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      $display("^^^---------------------------------");
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      $display("^^^---------------------------------");
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      $stop();
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    end
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endmodule
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