OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [avalon_lib/] [sim/] [tests/] [tb_ast_monitor/] [tb_ast_monitor.sv] - Blame information for rev 33

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 32 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
 
29
module tb_top();
30
 
31
  // --------------------------------------------------------------------
32
  // test bench clock & reset
33
  wire clk_100mhz;
34
  wire tb_clk = clk_100mhz;
35
  wire tb_rst;
36
 
37
  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
38
 
39
 
40
  // --------------------------------------------------------------------
41
  //
42
  wire tb_rst_s;
43
  wire clk    = tb_clk;
44
  wire reset  = tb_rst_s;
45
 
46
  sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
47
 
48
 
49
  // --------------------------------------------------------------------
50
  //
51
  import tb_ast_monitor_pkg::*;
52
 
53
 
54
  // --------------------------------------------------------------------
55
  //
56
  ast_if #(EW, CW, SW, NSW) src(.*);
57
  ast_if #(EW, CW, SW, NSW) sink(.*);
58
 
59
 
60
  // --------------------------------------------------------------------
61
  // sim models
62
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
63
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
64
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
65
 
66
 
67
  // --------------------------------------------------------------------
68
  //
69
  ast_monitor
70
    #(
71
      .ST_SYMBOL_W(ST_SYMBOL_W),
72
      .ST_NUMSYMBOLS(ST_NUMSYMBOLS),
73
      .USE_PACKET(USE_PACKET),
74
      .ST_READY_LATENCY(ST_READY_LATENCY),
75
      .USE_CHANNEL(USE_CHANNEL),
76
      .USE_ERROR(USE_ERROR),
77
      .USE_READY(USE_READY),
78
      .USE_VALID(USE_VALID),
79
      .USE_EMPTY(USE_EMPTY),
80
      .ST_ERROR_W(ST_ERROR_W),
81
      .ST_MAX_PACKET_SIZE(ST_MAX_PACKET_SIZE),
82
      .ST_MAX_CHANNELS(ST_MAX_CHANNELS)
83
    )
84
    ast_monitor_i(.sink(src), .src(sink), .*);
85
 
86 33 qaztronic
 
87 32 qaztronic
  // --------------------------------------------------------------------
88
  //
89
  ast_source
90
    #(
91
      .ST_SYMBOL_W(ST_SYMBOL_W),
92
      .ST_NUMSYMBOLS(ST_NUMSYMBOLS),
93
      .USE_PACKET(USE_PACKET),
94
      .ST_READY_LATENCY(ST_READY_LATENCY),
95
      .USE_CHANNEL(USE_CHANNEL),
96
      .USE_ERROR(USE_ERROR),
97
      .USE_READY(USE_READY),
98
      .USE_VALID(USE_VALID),
99
      .USE_EMPTY(USE_EMPTY),
100
      .ST_ERROR_W(ST_ERROR_W),
101
      .ST_MAX_CHANNELS(ST_MAX_CHANNELS)
102
    )
103
    ast_source_i(.*);
104
 
105
 
106
  // --------------------------------------------------------------------
107
  //
108
  ast_sink
109
    #(
110
      .ST_SYMBOL_W(ST_SYMBOL_W),
111
      .ST_NUMSYMBOLS(ST_NUMSYMBOLS),
112
      .USE_PACKET(USE_PACKET),
113
      .ST_READY_LATENCY(ST_READY_LATENCY),
114
      .USE_CHANNEL(USE_CHANNEL),
115
      .USE_ERROR(USE_ERROR),
116
      .USE_READY(USE_READY),
117
      .USE_VALID(USE_VALID),
118
      .USE_EMPTY(USE_EMPTY),
119
      .ST_ERROR_W(ST_ERROR_W),
120
      .ST_MAX_CHANNELS(ST_MAX_CHANNELS)
121
    )
122
    ast_sink_i(.*);
123
 
124 33 qaztronic
 
125
 
126 32 qaztronic
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
127
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
128
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
129
  // sim models
130
  // --------------------------------------------------------------------
131
 
132
 
133
 
134
  // --------------------------------------------------------------------
135
  // test
136
  the_test test( tb_clk, tb_rst );
137
 
138
  initial
139
    begin
140
 
141
      test.run_the_test();
142
 
143
      $display("^^^---------------------------------");
144
      $display("^^^ %16.t | Testbench done.", $time);
145
      $display("^^^---------------------------------");
146
 
147
      $display("^^^---------------------------------");
148
 
149
      $stop();
150
 
151
    end
152
 
153
endmodule
154
 
155
 
156
 

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.