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//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

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//////////////////////////////////////////////////////////////////////

module tb_top();

  // --------------------------------------------------------------------

  // test bench clock & reset

  wire clk_100mhz;

  wire tb_clk = clk_100mhz;

  wire tb_rst;

  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);

  // --------------------------------------------------------------------

  //

  wire tb_rst_s;

  wire clk    = tb_clk;

  wire reset  = tb_rst_s;

  sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);

  // --------------------------------------------------------------------

  //

  import tb_ast_monitor_pkg::*;

  // --------------------------------------------------------------------

  //

  ast_if #(EW, CW, SW, NSW) src(.*);

  ast_if #(EW, CW, SW, NSW) sink(.*);

  // --------------------------------------------------------------------

  // sim models

  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |

  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------

  //

  ast_monitor

    #(

      .ST_SYMBOL_W(ST_SYMBOL_W),

      .ST_NUMSYMBOLS(ST_NUMSYMBOLS),

      .USE_PACKET(USE_PACKET),

      .ST_READY_LATENCY(ST_READY_LATENCY),

      .USE_CHANNEL(USE_CHANNEL),

      .USE_ERROR(USE_ERROR),

      .USE_READY(USE_READY),

      .USE_VALID(USE_VALID),

      .USE_EMPTY(USE_EMPTY),

      .ST_ERROR_W(ST_ERROR_W),

      .ST_MAX_PACKET_SIZE(ST_MAX_PACKET_SIZE),

      .ST_MAX_CHANNELS(ST_MAX_CHANNELS)

    )

    ast_monitor_i(.sink(src), .src(sink), .*);

  // --------------------------------------------------------------------

  //

  ast_source

    #(

      .ST_SYMBOL_W(ST_SYMBOL_W),

      .ST_NUMSYMBOLS(ST_NUMSYMBOLS),

      .USE_PACKET(USE_PACKET),

      .ST_READY_LATENCY(ST_READY_LATENCY),

      .USE_CHANNEL(USE_CHANNEL),

      .USE_ERROR(USE_ERROR),

      .USE_READY(USE_READY),

      .USE_VALID(USE_VALID),

      .USE_EMPTY(USE_EMPTY),

      .ST_ERROR_W(ST_ERROR_W),

      .ST_MAX_CHANNELS(ST_MAX_CHANNELS)

    )

    ast_source_i(.*);

  // --------------------------------------------------------------------

  //

  ast_sink

    #(

      .ST_SYMBOL_W(ST_SYMBOL_W),

      .ST_NUMSYMBOLS(ST_NUMSYMBOLS),

      .USE_PACKET(USE_PACKET),

      .ST_READY_LATENCY(ST_READY_LATENCY),

      .USE_CHANNEL(USE_CHANNEL),

      .USE_ERROR(USE_ERROR),

      .USE_READY(USE_READY),

      .USE_VALID(USE_VALID),

      .USE_EMPTY(USE_EMPTY),

      .ST_ERROR_W(ST_ERROR_W),

      .ST_MAX_CHANNELS(ST_MAX_CHANNELS)

    )

    ast_sink_i(.*);

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\

  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |

  // sim models

  // --------------------------------------------------------------------

  // --------------------------------------------------------------------

  // test

  the_test test( tb_clk, tb_rst );

  initial

    begin

      test.run_the_test();

      $display("^^^---------------------------------");

      $display("^^^ %16.t | Testbench done.", $time);

      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule