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[/] [qaz_libs/] [trunk/] [avalon_lib/] [src/] [fifo_to_ast.sv] - Blame information for rev 35

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1 35 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  fifo_to_ast
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  #(
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    READYLATENCY,
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    EW = 1, // error signal width in bits.
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    CW = 1, // channel width in bits.
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    SW = 8, // Data symbol width in bits. Should be 8 for byte oriented interfaces.
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    NSB, // Numbers of symbols per beat
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    NSB_L = (NSB == 1) ? 1 : $clog2(NSB), // empty width
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    D = 2,
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    UB = $clog2(D)
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  )
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  (
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    output            wr_full,
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    input             wr_en,
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    ast_if            ast_in,
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    ast_if            ast_out,
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    input             clk,
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    input             reset
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  );
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  // --------------------------------------------------------------------
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  //
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  reg [READYLATENCY:0] ready_r;
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  wire ready_cycle = ready_r[READYLATENCY];
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  always_ff @(posedge clk)
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    if(reset)
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      ready_r <= 0;
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    else
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      ready_r <= {ready_r[READYLATENCY-1:0], ast_out.ready};
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  // --------------------------------------------------------------------
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  //
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  localparam FW = (SW*NSB) + 1 + 1 + NSB_L + CW + EW;
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  // --------------------------------------------------------------------
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  //
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  wire [FW-1:0] wr_data =
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                { ast_in.channel
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                , ast_in.error
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                , ast_in.data
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                , ast_in.empty
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                , ast_in.endofpacket
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                , ast_in.startofpacket
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                };
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  wire [FW-1:0] rd_data;
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  assign  { ast_out.channel
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          , ast_out.error
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          , ast_out.data
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          , ast_out.empty
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          , ast_out.endofpacket
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          , ast_out.startofpacket
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          } = rd_data;
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  // --------------------------------------------------------------------
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  //
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  wire rd_empty;
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  wire rd_en = ready_cycle & ~rd_empty;
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  wire [UB:0] count;
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  sync_fifo #(.W(FW), .D(D))
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    sync_fifo_i(.*);
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  // --------------------------------------------------------------------
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  //
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  assign ast_out.valid = rd_en;
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// --------------------------------------------------------------------
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//
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endmodule
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