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//////////////////////////////////////////////////////////////////////

module

  axi4_checker

  #(

    A = 32, // address bus width

    N = 8,  // data bus width in bytes

    I = 1,   // ID width

    MAXRBURSTS    = 16,

    MAXWBURSTS    = 16,

    MAXWAITS      = 16,

    RecommendOn   = 1'b1,

    RecMaxWaitOn  = 1'b1,

    EXMON_WIDTH   = 4

  )

  (

    axi4_if axi4_in

  );

  //---------------------------------------------------

  //

  localparam AWUSER_MAX = 0;

  localparam WUSER_MAX = 0;

  localparam BUSER_MAX = 0;

  localparam ARUSER_MAX = 0;

  localparam RUSER_MAX = 0;

  //---------------------------------------------------

  //

  // INDEX:        - Global Signals

  // =====

  wire                ACLK = axi4_in.aclk;     // AXI Clock

  wire                ARESETn = axi4_in.aresetn;  // AXI Reset

  // INDEX:        - Write Address Channel

  // =====

  wire      [(I-1):0] AWID = axi4_in.awid;

  wire      [(A-1):0] AWADDR = axi4_in.awaddr;

  wire          [7:0] AWLEN = axi4_in.awlen;

  wire          [2:0] AWSIZE = axi4_in.awsize;

  wire          [1:0] AWBURST = axi4_in.awburst;

  wire          [3:0] AWCACHE = axi4_in.awcache;

  wire          [2:0] AWPROT = axi4_in.awprot;

  wire          [3:0] AWQOS = axi4_in.awqos;

  wire          [3:0] AWREGION = axi4_in.awregion;

  wire                AWLOCK = axi4_in.awlock;

  wire [AWUSER_MAX:0] AWUSER = 0;

  wire                AWVALID = axi4_in.awvalid;

  wire                AWREADY = axi4_in.awready;

  // INDEX:        - Write Data Channel

  // =====

  wire    [(8*N)-1:0] WDATA = axi4_in.wdata;

  wire        [N-1:0] WSTRB = axi4_in.wstrb;

  wire  [WUSER_MAX:0] WUSER = 0;

  wire                WLAST = axi4_in.wlast;

  wire                WVALID = axi4_in.wvalid;

  wire                WREADY = axi4_in.wready;

  // INDEX:        - Write Response Channel

  // =====

  wire      [(I-1):0] BID = axi4_in.bid;

  wire          [1:0] BRESP = axi4_in.bresp;

  wire  [BUSER_MAX:0] BUSER = 0;

  wire                BVALID = axi4_in.bvalid;

  wire                BREADY = axi4_in.bready;

  // INDEX:        - Read Address Channel

  // =====

  wire      [(I-1):0] ARID = axi4_in.arid;

  wire      [(A-1):0] ARADDR = axi4_in.araddr;

  wire          [7:0] ARLEN = axi4_in.arlen;

  wire          [2:0] ARSIZE = axi4_in.arsize;

  wire          [1:0] ARBURST = axi4_in.arburst;

  wire          [3:0] ARCACHE = axi4_in.arcache;

  wire          [3:0] ARQOS = axi4_in.arqos;

  wire          [3:0] ARREGION = axi4_in.arregion;

  wire          [2:0] ARPROT = axi4_in.arprot;

  wire                ARLOCK = axi4_in.arlock;

  wire [ARUSER_MAX:0] ARUSER = 0;

  wire                ARVALID = axi4_in.arvalid;

  wire                ARREADY = axi4_in.arready;

  // INDEX:        - Read Data Channel

  // =====

  wire      [(I-1):0] RID = axi4_in.rid;

  wire    [(8*N)-1:0] RDATA = axi4_in.rdata;

  wire          [1:0] RRESP = axi4_in.rresp;

  wire  [RUSER_MAX:0] RUSER = 0;

  wire                RLAST = axi4_in.rlast;

  wire                RVALID = axi4_in.rvalid;

  wire                RREADY = axi4_in.rready;

  // INDEX:        - Low Power Interface

  // =====

  wire                CACTIVE = 1;

  wire                CSYSREQ = 0;

  wire                CSYSACK = 0;

  //---------------------------------------------------

  //

  Axi4PC_ace

    #(

      // Set DATA_WIDTH to the data-bus width required

      .DATA_WIDTH(8*N), // = 64;         // data bus width, default = 64-bit

      // Select the number of channel ID bits required

      .WID_WIDTH(I), // = 4;            // (A|W|R|B)ID width

      .RID_WIDTH(I), // = 4;            // (A|W|R|B)ID width

      // Select the size of the USER buses, default = 32-bit

      .AWUSER_WIDTH(0), // = 32;       // width of the user AW sideband field

      .WUSER_WIDTH(0), //  = 32;       // width of the user W  sideband field

      .BUSER_WIDTH(0), //  = 32;       // width of the user B  sideband field

      .ARUSER_WIDTH(0), // = 32;       // width of the user AR sideband field

      .RUSER_WIDTH(0), //  = 32;       // width of the user R  sideband field

      // Size of CAMs for storing outstanding read bursts, this should match or

      // exceed the number of outstanding read addresses accepted into the slave

      // interface

      .MAXRBURSTS(MAXRBURSTS), // = 16;

      // Size of CAMs for storing outstanding write bursts, this should match or

      // exceed the number of outstanding write bursts into the slave  interface

      .MAXWBURSTS(MAXWBURSTS), // = 16;

      // Maximum number of cycles between VALID -> READY high before a warning is

      // generated

      .MAXWAITS(MAXWAITS), // = 16;

      // Recommended Rules Enable

      // enable/disable reporting of all  AXI4_REC*_* rules

      .RecommendOn(RecommendOn), //   = 1'b1;

      // enable/disable reporting of just AXI4_REC*_MAX_WAIT rules

      .RecMaxWaitOn(RecMaxWaitOn), //  = 1'b1;

      // Set the protocol - used to disable some AXI4 checks for ACE

      // .PROTOCOL(PROTOCOL), // = `AXI4PC_AMBA_AXI4;

      // Set ADDR_WIDTH to the address-bus width required

      .ADDR_WIDTH(A), // = 32;        // address bus width, default = 32-bit

      // Set EXMON_WIDTH to the exclusive access monitor width required

      .EXMON_WIDTH(EXMON_WIDTH)  // = 4;        // exclusive access width, default = 4-bit

    )

    Axi4PC_ace_i(.*);

//---------------------------------------------------

//

endmodule