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[/] [qaz_libs/] [trunk/] [axi4_lib/] [sim/] [src/] [axi4_bfm/] [axi4_slave_bfm_if.sv] - Blame information for rev 29

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1 29 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
27
 
28
 
29
interface
30
  axi4_slave_bfm_if
31
  #(
32
    A = 32, // address bus width
33
    N = 8,  // data bus width in bytes
34
    I = 1   // ID width
35
  )
36
  (
37
    axi4_if axi4_m,
38
    input   aresetn,
39
    input   aclk
40
  );
41
 
42
  logic [(A-1):0]    araddr;
43
  logic [1:0]        arburst;
44
  logic [3:0]        arcache;
45
  logic [(I-1):0]    arid;
46
  logic [7:0]        arlen;
47
  logic              arlock;
48
  logic [2:0]        arprot;
49
  logic [3:0]        arqos;
50
  logic              arready;
51
  logic [3:0]        arregion;
52
  logic [2:0]        arsize;
53
  logic              arvalid;
54
  logic [(A-1):0]    awaddr;
55
  logic [1:0]        awburst;
56
  logic [3:0]        awcache;
57
  logic [(I-1):0]    awid;
58
  logic [7:0]        awlen;
59
  logic              awlock;
60
  logic [2:0]        awprot;
61
  logic [3:0]        awqos;
62
  logic              awready;
63
  logic [3:0]        awregion;
64
  logic [2:0]        awsize;
65
  logic              awvalid;
66
  logic [(I-1):0]    bid;
67
  logic              bready;
68
  logic [1:0]        bresp;
69
  logic              bvalid;
70
  logic [(8*N)-1:0]  rdata;
71
  logic [(I-1):0]    rid;
72
  logic              rlast;
73
  logic              rready;
74
  logic [1:0]        rresp;
75
  logic              rvalid;
76
  logic [(8*N)-1:0]  wdata;
77
  logic [(I-1):0]    wid;
78
  logic              wlast;
79
  logic              wready;
80
  logic [N-1:0]      wstrb;
81
  logic              wvalid;
82
 
83
 
84
  // --------------------------------------------------------------------
85
  //
86
  default clocking cb @(posedge aclk);
87
    input   arid;
88
    input   araddr;
89
    input   arburst;
90
    input   arcache;
91
    input   awid;
92
    input   arlen;
93
    input   arlock;
94
    input   arprot;
95
    input   arqos;
96
    output  arready;
97
    input   arregion;
98
    input   arsize;
99
    input   arvalid;
100
    input   awaddr;
101
    input   awburst;
102
    input   awcache;
103
    input   awlen;
104
    input   awlock;
105
    input   awprot;
106
    input   awqos;
107
    output  awready;
108
    input   awregion;
109
    input   awsize;
110
    input   awvalid;
111
    input   bready;
112
    output  bid;
113
    output  bresp;
114
    output  bvalid;
115
    output  rdata;
116
    output  rid;
117
    output  rlast;
118
    input   rready;
119
    output  rresp;
120
    output  rvalid;
121
    input   wdata;
122
    input   wid;
123
    input   wlast;
124
    output  wready;
125
    input   wstrb;
126
    input   wvalid;
127
    input   aresetn;
128
    input   aclk;
129
  endclocking
130
 
131
 
132
  // --------------------------------------------------------------------
133
  //
134
  assign arid           = axi4_m.arid;
135
  assign araddr         = axi4_m.araddr;
136
  assign arburst        = axi4_m.arburst;
137
  assign arcache        = axi4_m.arcache;
138
  assign awid           = axi4_m.awid;
139
  assign arlen          = axi4_m.arlen;
140
  assign arlock         = axi4_m.arlock;
141
  assign arprot         = axi4_m.arprot;
142
  assign arqos          = axi4_m.arqos;
143
  assign axi4_m.arready = arready;
144
  assign arregion       = axi4_m.arregion;
145
  assign arsize         = axi4_m.arsize;
146
  assign arvalid        = axi4_m.arvalid;
147
  assign awaddr         = axi4_m.awaddr;
148
  assign awburst        = axi4_m.awburst;
149
  assign awcache        = axi4_m.awcache;
150
  assign awlen          = axi4_m.awlen;
151
  assign awlock         = axi4_m.awlock;
152
  assign awprot         = axi4_m.awprot;
153
  assign awqos          = axi4_m.awqos;
154
  assign axi4_m.awready = awready;
155
  assign awregion       = axi4_m.awregion;
156
  assign awsize         = axi4_m.awsize;
157
  assign awvalid        = axi4_m.awvalid;
158
  assign bready         = axi4_m.bready;
159
  assign axi4_m.bid     = bid;
160
  assign axi4_m.bresp   = bresp;
161
  assign axi4_m.bvalid  = bvalid;
162
  assign axi4_m.rdata   = rdata;
163
  assign axi4_m.rid     = rid;
164
  assign axi4_m.rlast   = rlast;
165
  assign rready         = axi4_m.rready;
166
  assign axi4_m.rresp   = rresp;
167
  assign axi4_m.rvalid  = rvalid;
168
  assign wdata          = axi4_m.wdata;
169
  assign wlast          = axi4_m.wlast;
170
  assign axi4_m.wready  = wready;
171
  assign wstrb          = axi4_m.wstrb;
172
  assign wvalid         = axi4_m.wvalid;
173
 
174
 
175
  // --------------------------------------------------------------------
176
  //
177
  function void
178
    ar_default;
179
 
180
    cb.arready <= 0;
181
 
182
  endfunction: ar_default
183
 
184
 
185
  // --------------------------------------------------------------------
186
  //
187
  function void
188
    aw_default;
189
 
190
    cb.awready <= 0;
191
 
192
  endfunction: aw_default
193
 
194
 
195
  // --------------------------------------------------------------------
196
  //
197
  function void
198
    r_default;
199
 
200
    cb.rdata  <= 'bx;
201
    cb.rid    <= 'bx;
202
    cb.rlast  <= 'bx;
203
    cb.rresp  <= 0;
204
    cb.rvalid <= 0;
205
 
206
  endfunction: r_default
207
 
208
 
209
  // --------------------------------------------------------------------
210
  //
211
  function void
212
    w_default;
213
 
214
    cb.wready  <= 0;
215
 
216
  endfunction: w_default
217
 
218
 
219
  // --------------------------------------------------------------------
220
  //
221
  function void
222
    b_default;
223
 
224
    cb.bid     <= 0;
225
    cb.bresp   <= 0;
226
    cb.bvalid  <= 0;
227
 
228
  endfunction: b_default
229
 
230
 
231
  // --------------------------------------------------------------------
232
  //
233
  function void
234
    init;
235
 
236
    ar_default();
237
    r_default();
238
    aw_default();
239
    w_default();
240
    b_default();
241
 
242
  endfunction: init
243
 
244
 
245
  // --------------------------------------------------------------------
246
  //
247
  task
248
    zero_cycle_delay;
249
 
250
    ##0;
251
 
252
  endtask: zero_cycle_delay
253
 
254
 
255
  // --------------------------------------------------------------------
256
  //
257
  import tb_bfm_pkg::*;
258
  import axi4_transaction_pkg::*;
259
 
260
 
261
  // --------------------------------------------------------------------
262
  //
263
  class r_slave_transaction_class #(A = 32, N = 8, I = 1)
264
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
265
 
266
    // --------------------------------------------------------------------
267
    //
268
    task automatic
269
      transaction
270
      (
271
        ref T tr_h
272
      );
273
 
274
      ->this.start;
275
 
276
      foreach(tr_h.payload_h.w[i])
277
      begin
278
        ##(tr_h.delay_h.next());
279
 
280
        cb.rdata   <= tr_h.payload_h.w[i];
281
        cb.rresp   <= tr_h.resp;
282
        cb.rid     <= tr_h.id;
283
 
284
        if(i < tr_h.payload_h.w.size - 1)
285
          cb.rlast   <= 0;
286
        else
287
          cb.rlast   <= 1;
288
 
289
        cb.rvalid  <= 1;
290
        ##1;
291
 
292
        wait(cb.rready);
293
        ##0;
294
 
295
        $display("^^^ %16.t | %m   | slave R transaction  | %d | 0x%016x |", $time, i, tr_h.payload_h.w[i]);
296
        r_default();
297
      end
298
 
299
      ->this.done;
300
 
301
    endtask: transaction
302
 
303
 
304
  // --------------------------------------------------------------------
305
  //
306
  endclass: r_slave_transaction_class
307
 
308
 
309
  // --------------------------------------------------------------------
310
  //
311
  r_slave_transaction_class #(.A(A), .N(N), .I(I)) r_h;
312
 
313
  class ar_slave_transaction_class #(A = 32, N = 8, I = 1)
314
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
315
 
316
    // --------------------------------------------------------------------
317
    //
318
    task automatic
319
      transaction
320
      (
321
        ref T tr_h
322
      );
323
 
324
      ->this.start;
325
 
326
      ##(tr_h.delay_h.next());
327
 
328
      cb.arready  <= 1;
329
      ##1;
330
 
331
      wait(cb.arvalid);
332
 
333
      ##0;
334
      r_h.put(tr_h);
335
      ar_default();
336
 
337
      $display("^^^ %16.t | %m   | slave AR transaction @ 0x%08x  | 0x%016x |", $time, tr_h.addr, tr_h.payload_h.w[0]);
338
 
339
      ->this.done;
340
 
341
    endtask: transaction
342
 
343
 
344
  // --------------------------------------------------------------------
345
  //
346
  endclass: ar_slave_transaction_class
347
 
348
 
349
  // --------------------------------------------------------------------
350
  //
351
  class aw_slave_transaction_class #(A = 32, N = 8, I = 1)
352
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
353
 
354
    semaphore aw_semaphore;
355
 
356
 
357
    //--------------------------------------------------------------------
358
    function new;
359
 
360
      super.new();
361
      this.aw_semaphore = new(0);
362
 
363
    endfunction: new
364
 
365
 
366
    // --------------------------------------------------------------------
367
    //
368
    task automatic
369
      transaction
370
      (
371
        ref T tr_h
372
      );
373
 
374
      ->this.start;
375
 
376
      ##(tr_h.delay_h.next());
377
 
378
      cb.awready  <= 1;
379
      ##1;
380
 
381
      wait(cb.awvalid);
382
 
383
      ##0;
384
      this.aw_semaphore.put();
385
      aw_default();
386
 
387
      $display("^^^ %16.t | %m   | slave AW transaction @ 0x%08x  | 0x%016x |", $time, tr_h.addr, tr_h.payload_h.w[0]);
388
 
389
      ->this.done;
390
 
391
    endtask: transaction
392
 
393
  // --------------------------------------------------------------------
394
  //
395
  endclass: aw_slave_transaction_class
396
 
397
 
398
  // --------------------------------------------------------------------
399
  //
400
  aw_slave_transaction_class #(.A(A), .N(N), .I(I)) aw_h;
401
 
402
  class b_slave_transaction_class #(A = 32, N = 8, I = 1)
403
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
404
 
405
    // --------------------------------------------------------------------
406
    //
407
    task automatic
408
      transaction
409
      (
410
        ref T tr_h
411
      );
412
 
413
      ->this.start;
414
 
415
      // Error: AXI4_ERRS_BRESP_AW: A slave must not give a write response before the write address.
416
      //        Spec: section A3.3.1 and figure A3-7.
417
      aw_h.aw_semaphore.get();  // better way to do this???
418
 
419
      ##(tr_h.delay_h.next());
420
 
421
      cb.bresp   <= tr_h.resp;
422
      cb.bid     <= tr_h.id;
423
 
424
      cb.bvalid  <= 1;
425
      ##1;
426
 
427
      wait(cb.bready);
428
      ##0;
429
 
430
      $display("^^^ %16.t | %m | slave B transaction  |", $time);
431
      b_default();
432
 
433
      ->this.done;
434
 
435
    endtask: transaction
436
 
437
  // --------------------------------------------------------------------
438
  //
439
  endclass: b_slave_transaction_class
440
 
441
 
442
  // --------------------------------------------------------------------
443
  //
444
  b_slave_transaction_class #(.A(A), .N(N), .I(I)) b_h;
445
 
446
  class w_slave_transaction_class #(A = 32, N = 8, I = 1)
447
    extends tb_blocking_transaction_q_class #(axi4_transaction_class #(.A(A), .N(N), .I(I)));
448
 
449
    // --------------------------------------------------------------------
450
    //
451
    task automatic
452
      transaction
453
      (
454
        ref T tr_h
455
      );
456
 
457
      ->this.start;
458
 
459
      tr_h.data_h = new(tr_h.len);
460
 
461
      foreach(tr_h.payload_h.w[i])
462
      begin
463
        ##(tr_h.delay_h.next());
464
 
465
        cb.wready  <= 1;
466
        ##1;
467
 
468
        wait(cb.wvalid);
469
        ##0;
470
 
471
        tr_h.data_h.w[i] <= cb.wdata;
472
        $display("^^^ %16.t | %m   | slave W transaction  | %d | 0x%016x |", $time, i, cb.wdata);
473
        w_default();
474
      end
475
 
476
      b_h.put(tr_h);
477
 
478
      ->this.done;
479
 
480
    endtask: transaction
481
 
482
 
483
  // --------------------------------------------------------------------
484
  //
485
  endclass: w_slave_transaction_class
486
 
487
 
488
  // --------------------------------------------------------------------
489
  //
490
  ar_slave_transaction_class #(.A(A), .N(N), .I(I)) ar_h;
491
  w_slave_transaction_class #(.A(A), .N(N), .I(I)) w_h;
492
 
493
  initial
494
  begin
495
    init();
496
    ar_h = new;
497
    ar_h.init();
498
    r_h = new;
499
    r_h.init();
500
    aw_h = new;
501
    aw_h.init();
502
    w_h = new;
503
    w_h.init();
504
    b_h = new;
505
    b_h.init();
506
  end
507
 
508
 
509
// --------------------------------------------------------------------
510
//
511
 
512
endinterface
513
 
514
 

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