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[/] [qaz_libs/] [trunk/] [axi4_lib/] [sim/] [src/] [axi4_models/] [tb_axi4_multi_port_memory.sv] - Blame information for rev 31

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1 31 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  tb_axi4_multi_port_memory
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  #(
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    A     = 32, // address bus width
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    N     = 8,  // data bus width in bytes
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    I     = 1,   // ID width
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    PORTS,
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    MAXWAITS = 256,
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    type WORD_T = byte
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  )
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  (
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    axi4_if     axi4_s[PORTS],
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    input       aclk,
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    input       aresetn
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  );
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  // --------------------------------------------------------------------
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  //
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  import axis_bfm_pkg::*;
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  import axi4_memory_pkg::*;
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  import axi4_arbiter_pkg::*;
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  // --------------------------------------------------------------------
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  //
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  axi4_if #(.A(A), .N(N), .I(I)) axi4_bus(.*);
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  // --------------------------------------------------------------------
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  //
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  axi4_arbiter_class #(A, N, I) arb_h;
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  axi4_memory_class #(A, N, I, WORD_T) m_h;
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  initial
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  begin
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    arb_h = new(axi4_s, axi4_bus);
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    m_h = new(axi4_bus);
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  end
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  // --------------------------------------------------------------------
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  //
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  axi4_checker #(.A(A), .N(N), .MAXWAITS(MAXWAITS))
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    axi4_bus_checker(.axi4_in(axi4_bus));
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  // --------------------------------------------------------------------
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  //
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  generate
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    begin: axi4_s_cherkers
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      for(genvar j = 0; j < PORTS; j++)
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        axi4_checker #(.A(A), .N(N), .MAXWAITS(MAXWAITS))
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          axi4_checker_i(.axi4_in(axi4_s[j]));
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    end
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  endgenerate
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// --------------------------------------------------------------------
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//
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endmodule
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