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//////////////////////////////////////////////////////////////////////

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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//// Public License as published by the Free Software Foundation; ////

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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

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//////////////////////////////////////////////////////////////////////

module tb_top();

  // --------------------------------------------------------------------

  // test bench clock & reset

  wire clk_100mhz;

  wire tb_clk = clk_100mhz;

  wire tb_rst;

  wire aclk = tb_clk;

  wire aresetn = ~tb_rst;

  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);

  // --------------------------------------------------------------------

  //

  localparam A = 32;

  localparam N = 8;

  // --------------------------------------------------------------------

  //

  axi4_if #(.A(A), .N(N))

    axi4_s(.*);

  // --------------------------------------------------------------------

  //

  // --------------------------------------------------------------------

  // sim models

  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |

  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------

  //

  axi4_checker #(.A(A), .N(N))

    axi4_s_check(.axi4_in(axi4_s));

  // // --------------------------------------------------------------------

  // //

  // axi4_master_bfm_if #(.A(A), .N(N))

    // tb_axi4_m(.axi4_s(axi4_s), .*);

  // --------------------------------------------------------------------

  //

  import axi4_bfm_pkg::*;

  axi4_master_bfm_class bfm;

  initial

    bfm = new(axi4_s);

  // --------------------------------------------------------------------

  //

  import axi4_memory_pkg::*;

  axi4_memory_class axi4_memory;

  initial

    axi4_memory = new(axi4_s);

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\

  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |

  // sim models

  // --------------------------------------------------------------------

  // --------------------------------------------------------------------

  //  debug wires

  // --------------------------------------------------------------------

  // test

  the_test test( tb_clk, tb_rst );

  initial

    begin

      test.run_the_test();

      $display("^^^---------------------------------");

      $display("^^^ %16.t | Testbench done.", $time);

      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule