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[/] [qaz_libs/] [trunk/] [axi4_lib/] [sim/] [tests/] [debug_register_slice/] [the_test.sv] - Blame information for rev 29

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1 29 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ps/1ps
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module
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  the_test(
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            input tb_clk,
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            input tb_rst
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          );
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  // --------------------------------------------------------------------
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  //
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  localparam A = tb_top.A;
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  localparam N = tb_top.N;
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  // --------------------------------------------------------------------
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  //
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  import axi4_transaction_pkg::*;
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  axi4_payload_class payload_h;
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  // --------------------------------------------------------------------
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  //
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  logic [(8*N)-1:0] data[];
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  logic [1:0] resp;
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  task run_the_test;
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    // --------------------------------------------------------------------
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    // insert test below
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    // --------------------------------------------------------------------
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    $display("^^^---------------------------------");
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    $display("^^^ %16.t | Testbench begun.\n", $time);
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    $display("^^^---------------------------------");
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    // --------------------------------------------------------------------
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    tb_top.tb.timeout_stop(20us);
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    // tb_top.tb.timeout_stop(300ns);
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    // --------------------------------------------------------------------
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    wait(~tb_rst);
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    // --------------------------------------------------------------------
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    #100ns;
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    repeat(5)
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    begin
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      tb_top.bfm.basic_read(32'h1234_0000, 3, data, resp);
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      foreach(data[i])
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        $display("^^^ %16.t | %d | 0x%016x |", $time, i, data[i]);
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    end
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    tb_top.bfm.basic_read(32'habcd_0000, 0, data, resp);
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    $display("^^^ %16.t | 0x%016x |", $time, data[0]);
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    // // --------------------------------------------------------------------
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    // tb_top.bfm.basic_read(32'habcd_0000, 0, data, resp);
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    // $display("^^^ %16.t | 0x%016x |", $time, data[0]);
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    // --------------------------------------------------------------------
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    #100ns;
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    data = new[1];
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    data[0] = 64'habba_beef_cafe_1a7e;
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    tb_top.bfm.basic_write(32'h1234_0000, 0, data, resp);
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    // --------------------------------------------------------------------
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    #100ns;
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    repeat(5)
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    begin
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      tb_top.bfm.basic_random_write(32'habcd_0000, 0, resp);
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    end
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    // --------------------------------------------------------------------
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    #100ns;
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    repeat(5)
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    begin
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      tb_top.bfm.basic_random_write(32'habcd_0000, 3, resp);
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    end
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    // --------------------------------------------------------------------
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    #100ns;
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    // --------------------------------------------------------------------
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    // insert test above
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    // --------------------------------------------------------------------
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  endtask
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endmodule
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