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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_if.sv] - Blame information for rev 29

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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interface
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  axi4_if
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  #(
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    A = 32, // address bus width
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    N = 8,  // data bus width in bytes
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    I = 1   // ID width
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  )
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  (
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    input           aresetn,
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    input           aclk
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  );
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  logic [(A-1):0]    araddr;
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  logic [1:0]        arburst;
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  logic [3:0]        arcache;
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  logic [(I-1):0]    arid;
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  logic [7:0]        arlen;
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  logic              arlock;
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  logic [2:0]        arprot;
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  logic [3:0]        arqos;
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  logic              arready;
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  logic [3:0]        arregion;
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  logic [2:0]        arsize;
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  logic              arvalid;
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  logic [(A-1):0]    awaddr;
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  logic [1:0]        awburst;
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  logic [3:0]        awcache;
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  logic [(I-1):0]    awid;
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  logic [7:0]        awlen;
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  logic              awlock;
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  logic [2:0]        awprot;
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  logic [3:0]        awqos;
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  logic              awready;
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  logic [3:0]        awregion;
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  logic [2:0]        awsize;
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  logic              awvalid;
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  logic [(I-1):0]    bid;
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  logic              bready;
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  logic [1:0]        bresp;
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  logic              bvalid;
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  logic [(8*N)-1:0]  rdata;
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  logic [(I-1):0]    rid;
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  logic              rlast;
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  logic              rready;
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  logic [1:0]        rresp;
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  logic              rvalid;
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  logic [(8*N)-1:0]  wdata;
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  logic [(I-1):0]    wid;
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  logic              wlast;
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  logic              wready;
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  logic [N-1:0]      wstrb;
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  logic              wvalid;
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// --------------------------------------------------------------------
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//
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endinterface
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