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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_m_to_write_fifos.sv] - Blame information for rev 31

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1 31 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axi4_m_to_write_fifos
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  #(
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    A     = 32, // address bus width
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    N     = 8,  // data bus width in bytes
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    I     = 1,  // ID width
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    W_D   = 32,
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    B_D   = 2,
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    AW_D  = 2,
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    WATERMARK = 0,
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    USE_ADVANCED_PROTOCOL = 0
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  )
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  (
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    axi4_if axi4_m,
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    axi4_if axi4_write_fifo,
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    output  aw_wr_full,
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    input   aw_wr_en,
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    output  w_wr_full,
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    input   w_wr_en,
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    output  w_topped_off,
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    output  w_watermark,
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    output  b_rd_empty,
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    input   b_rd_en,
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    input   aclk,
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    input   aresetn
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  );
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  // --------------------------------------------------------------------
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  //
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  localparam UB = $clog2(W_D);
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  // --------------------------------------------------------------------
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  //
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  localparam W_W =
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    8*N + // logic [(8*N)-1:0]  wdata;
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    I +   // logic [(I-1):0]    wid;
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    1 +   // logic              wlast;
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    N;    // logic [N-1:0]      wstrb;
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  localparam B_W =
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    I +   // logic [(I-1):0]    bid;
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    2;    // logic [1:0]        bresp;
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  localparam AX_BASIC_W =
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    A +  // logic [(A-1):0]    axaddr;
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    2 +  // logic [1:0]        axburst;
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    I +  // logic [(I-1):0]    axid;
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    8 +  // logic [7:0]        axlen;
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    3;   // logic [2:0]        axsize;
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  localparam AX_ADVANCED_W =
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    4 +   // logic [3:0]        axcache;
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    1 +   // logic              axlock;
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    3 +   // logic [2:0]        axprot;
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    4 +   // logic [3:0]        axqos;
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    4;    // logic [3:0]        axregion;
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  localparam AW_W = USE_ADVANCED_PROTOCOL ? AX_BASIC_W + AX_ADVANCED_W : AX_BASIC_W;
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  // --------------------------------------------------------------------
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  //
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  wire [AW_W-1:0] aw_rd_data;
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  wire [AW_W-1:0] aw_wr_data;
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  generate
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    begin: aw_data_gen
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      if(USE_ADVANCED_PROTOCOL)
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      begin
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        assign aw_wr_data =
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          {
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            axi4_write_fifo.awaddr,
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            axi4_write_fifo.awburst,
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            axi4_write_fifo.awid,
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            axi4_write_fifo.awlen,
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            axi4_write_fifo.awsize,
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            axi4_write_fifo.awcache,
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            axi4_write_fifo.awlock,
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            axi4_write_fifo.awprot,
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            axi4_write_fifo.awqos,
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            axi4_write_fifo.awregion
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          };
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        assign
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          {
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            axi4_m.awaddr,
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            axi4_m.awburst,
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            axi4_m.awid,
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            axi4_m.awlen,
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            axi4_m.awsize,
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            axi4_m.awcache,
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            axi4_m.awlock,
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            axi4_m.awprot,
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            axi4_m.awqos,
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            axi4_m.awregion
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          } = aw_rd_data;
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      end
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      else
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      begin
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        assign aw_wr_data =
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          {
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            axi4_write_fifo.awaddr,
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            axi4_write_fifo.awburst,
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            axi4_write_fifo.awid,
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            axi4_write_fifo.awlen,
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            axi4_write_fifo.awsize
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          };
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        assign
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          {
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            axi4_m.awaddr,
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            axi4_m.awburst,
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            axi4_m.awid,
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            axi4_m.awlen,
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            axi4_m.awsize
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          } = aw_rd_data;
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      end
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  //
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  wire aw_rd_empty;
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  wire aw_rd_en = axi4_m.awready & axi4_m.awvalid;
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  assign axi4_m.awvalid = ~aw_rd_empty;
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  sync_fifo #(.W(AW_W), .D(AW_D))
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    aw_fifo
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    (
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      .wr_full(aw_wr_full),
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      .wr_data(aw_wr_data),
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      .wr_en(aw_wr_en),
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      .rd_empty(aw_rd_empty),
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      .rd_data(aw_rd_data),
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      .rd_en(aw_rd_en),
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      .count(),
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      .clk(aclk),
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      .reset(~aresetn)
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    );
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  // --------------------------------------------------------------------
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  //
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  wire [W_W-1:0] w_rd_data;
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  wire [W_W-1:0] w_wr_data;
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  assign w_wr_data =
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    {
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      axi4_write_fifo.wdata,
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      axi4_write_fifo.wid,
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      axi4_write_fifo.wlast,
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      axi4_write_fifo.wstrb
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    };
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  assign
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    {
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      axi4_m.wdata,
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      axi4_m.wid,
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      axi4_m.wlast,
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      axi4_m.wstrb
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    } = w_rd_data;
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  // --------------------------------------------------------------------
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  //
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  wire [UB:0] w_count;
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  wire w_rd_empty;
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  wire w_rd_en = axi4_m.wready & axi4_m.wvalid;
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  assign axi4_m.wvalid = ~w_rd_empty;
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  sync_fifo #(.W(W_W), .D(W_D))
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    w_fifo
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    (
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      .wr_full(w_wr_full),
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      .wr_data(w_wr_data),
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      .wr_en(w_wr_en),
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      .rd_empty(w_rd_empty),
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      .rd_data(w_rd_data),
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      .rd_en(w_rd_en),
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      .count(w_count),
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      .clk(aclk),
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      .reset(~aresetn)
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    );
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  // --------------------------------------------------------------------
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  //
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  generate
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    begin: w_watermark_gen
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      if(WATERMARK == 0)
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      begin
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        assign w_topped_off = 1;
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        assign w_watermark = 0;
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      end
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      else
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      begin
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        reg w_topped_off_r;
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        assign w_topped_off = w_topped_off_r;
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        assign w_watermark = w_count > WATERMARK - 1;
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        always_ff @(posedge aclk)
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          if(~aresetn | w_rd_empty)
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            w_topped_off_r <= 0;
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          else if(w_watermark)
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            w_topped_off_r <= 1;
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      end
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  //
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  wire [B_W-1:0] b_rd_data;
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  wire [B_W-1:0] b_wr_data;
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  assign b_wr_data =
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    {
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      axi4_m.bid,
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      axi4_m.bresp
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    };
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  assign
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    {
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      axi4_write_fifo.bid,
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      axi4_write_fifo.bresp
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    } = b_rd_data;
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  // --------------------------------------------------------------------
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  //
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  wire b_wr_full;
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  wire b_wr_en = axi4_m.bready & axi4_m.bvalid;
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  assign axi4_m.bready = ~b_wr_full;
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  sync_fifo #(.W(B_W), .D(B_D))
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    b_fifo
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    (
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      .wr_full(b_wr_full),
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      .wr_data(b_wr_data),
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      .wr_en(b_wr_en),
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      .rd_empty(b_rd_empty),
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      .rd_data(b_rd_data),
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      .rd_en(b_rd_en),
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      .count(),
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      .clk(aclk),
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      .reset(~aresetn)
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    );
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// --------------------------------------------------------------------
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//
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endmodule
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