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[/] [qaz_libs/] [trunk/] [axi4_lib/] [src/] [axi4_to_axis_basic_dma.sv] - Blame information for rev 31

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1 31 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axi4_to_axis_basic_dma
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  #(
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    A, // address bus width
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    N,  // data bus width in bytes
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    I,  // ID width
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    BASE_ADDRESS, // must be on 4K boundry
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    BUFFER_SIZE,
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    BURST_LENGTH,
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    MAX_BURSTS, // max number of burst the FIFO can hold
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    BYTES_PER_TUSER = 0 //  bytes per tuser bit . Set to 0 for transfer based.
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  )
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  (
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    axi4_if axi4_m,
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    axis_if axis_out,
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    input   dma_enable,
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    input   aclk,
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    input   aresetn
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  );
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  // --------------------------------------------------------------------
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  //
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  localparam R_D = BURST_LENGTH * MAX_BURSTS;
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  localparam AR_D = 2;
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  localparam WATERMARK = BURST_LENGTH * (MAX_BURSTS - AR_D);
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  localparam STRIDE = N * BURST_LENGTH;
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  localparam ADDRESS_END = BASE_ADDRESS + BUFFER_SIZE;
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  localparam AR_STOP  = (BUFFER_SIZE % STRIDE)  ? ADDRESS_END - STRIDE  : ADDRESS_END;
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  localparam R_STOP   = (BUFFER_SIZE % N)       ? ADDRESS_END - N       : ADDRESS_END;
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  localparam U = N / BYTES_PER_TUSER;
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// --------------------------------------------------------------------
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// synthesis translate_off
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  localparam N_4K = 'h1000 / 'h8; // number of bytes in 4K
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  initial
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  begin
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    a_4k_mod_base_address: assert(BASE_ADDRESS % 'h1000 == 0) else $fatal;
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    a_4k_gt_eq_stride: assert(N_4K >= STRIDE) else $fatal;
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    a_4k_mod_stride: assert('h1000 % STRIDE == 0) else $fatal;
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    a_n: assert((N % BYTES_PER_TUSER == 0)) else $fatal;
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    a_buffer_size: assert(BUFFER_SIZE % N == 0) else $fatal;
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    a_bytes_per_tuser: assert(BYTES_PER_TUSER != 0) else $fatal; // need to fix
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  end
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// synthesis translate_on
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// --------------------------------------------------------------------
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  // --------------------------------------------------------------------
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  //
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  axi4_if #(.A(A), .N(N), .I(I))  axi4_read_fifo(.*);
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  axis_if #(.N(N), .U(U))         axis_in(.*);
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  // --------------------------------------------------------------------
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  //
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  reg [(A-1):0] araddr_r;
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  wire araddr_en = (araddr_r < AR_STOP);
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  wire r_watermark;
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  wire ar_wr_full;
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  wire ar_wr_en = ~ar_wr_full & ~r_watermark & araddr_en & dma_enable;
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  always_ff @(posedge aclk)
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    if(~aresetn | ~araddr_en)
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      araddr_r <= BASE_ADDRESS;
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    else if(ar_wr_en)
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      araddr_r <= araddr_r + STRIDE;
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  // --------------------------------------------------------------------
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  //
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  reg [(A-1):0] r_rd_addr;
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  wire r_rd_addr_en = (r_rd_addr < R_STOP);
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  wire r_rd_addr_start = (r_rd_addr == BASE_ADDRESS);
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  wire r_rd_addr_end   = (r_rd_addr == R_STOP);
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  wire r_rd_empty;
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  wire r_topped_off;
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  wire r_rd_en = ~r_rd_empty & r_rd_addr_en & axis_in.tready;
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  always_ff @(posedge aclk)
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    if(~aresetn | ~r_rd_addr_en)
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      r_rd_addr <= BASE_ADDRESS;
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    else if(r_rd_en)
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      r_rd_addr <= r_rd_addr + N;
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  // --------------------------------------------------------------------
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  //
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  axi4_m_to_read_fifos #(.A(A), .N(N), .I(I), .R_D(R_D), .AR_D(AR_D), .WATERMARK(WATERMARK))
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    axi4_m_to_read_fifos_i(.*);
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  // --------------------------------------------------------------------
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  //
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  assign axi4_read_fifo.araddr    = araddr_r;
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  assign axi4_read_fifo.arid      = 0;
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  assign axi4_read_fifo.arburst   = 2'b01;
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  assign axi4_read_fifo.arsize    = $clog2(N);
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  assign axi4_read_fifo.arlen     = BURST_LENGTH - 1;
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  assign axi4_read_fifo.rready    = 1;
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  // --------------------------------------------------------------------
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  //
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  assign axi4_m.awaddr    = 0;
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  assign axi4_m.awburst   = 0;
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  assign axi4_m.awcache   = 0;
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  assign axi4_m.awid      = 0;
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  assign axi4_m.awlen     = 0;
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  assign axi4_m.awlock    = 0;
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  assign axi4_m.awprot    = 0;
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  assign axi4_m.awqos     = 0;
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  assign axi4_m.awregion  = 0;
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  assign axi4_m.awsize    = 0;
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  assign axi4_m.awvalid   = 0;
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  assign axi4_m.bready    = 0;
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  assign axi4_m.wdata     = 0;
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  assign axi4_m.wid       = 0;
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  assign axi4_m.wlast     = 0;
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  assign axi4_m.wstrb     = 0;
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  assign axi4_m.wvalid    = 0;
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  // --------------------------------------------------------------------
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  //
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  assign axis_in.tvalid = ~r_rd_empty;
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  assign axis_in.tdata = axi4_read_fifo.rdata;
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  assign axis_in.tlast = axi4_read_fifo.rlast;
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  assign axis_in.tuser[0] = r_rd_addr_start;
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  assign axis_in.tuser[U-1:1] = 0; // need to fix
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  // --------------------------------------------------------------------
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  //
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  axis_register_slice #(.N(N), .U(U))
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    axis_register_slice_i(.*);
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// --------------------------------------------------------------------
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//
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endmodule
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