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//////////////////////////////////////////////////////////////////////

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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//// the original copyright notice and the associated disclaimer. ////

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//// This source file is free software; you can redistribute it   ////

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//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

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//////////////////////////////////////////////////////////////////////

module tb_top();

  // --------------------------------------------------------------------

  // test bench clock & reset

  wire clk_100mhz;

  wire tb_clk = clk_100mhz;

  wire tb_rst;

  wire aclk = tb_clk;

  wire aresetn = ~tb_rst;

  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);

  // --------------------------------------------------------------------

  //

  localparam A  = 32;

  localparam N  = 4;

  localparam MW = 3;  //  mux select width

  // --------------------------------------------------------------------

  //

  axi4_if #(.A(A), .N(N))

    axi4_s(.*);

  // --------------------------------------------------------------------

  //

  axi4_lite_register_if #(.N(N), .MW(MW))

    r_if(.*);

  assign r_if.register_in = r_if.register_out;

  // --------------------------------------------------------------------

  //

  axi4_lite_register_file #(.A(A), .N(N))

    dut(.*);

  // --------------------------------------------------------------------

  // sim models

  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |

  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------

  //

  axi4_checker #(.A(A), .N(N), .PROTOCOL(2'b10))

    axi4_s_check(.axi4_in(axi4_s));

  // --------------------------------------------------------------------

  //

  import axi4_lite_agent_pkg::*;

  // --------------------------------------------------------------------

  //

  axi4_master_bfm_if #(.A(A), .N(N))

    tb_axi4_m(.axi4_s(axi4_s), .*);

  // --------------------------------------------------------------------

  //

  axi4_lite_agent_class #(.A(A), .N(N), .MW(MW)) bfm;

  initial

    bfm = new(tb_axi4_m, r_if);

  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\

  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |

  // sim models

  // --------------------------------------------------------------------

  // --------------------------------------------------------------------

  //  debug wires

  // --------------------------------------------------------------------

  // test

  the_test test( tb_clk, tb_rst );

  initial

    begin

      test.run_the_test();

      $display("^^^---------------------------------");

      $display("^^^ %16.t | Testbench done.", $time);

      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule