OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [axi4_lite_lib/] [src/] [axi4_lite_register_file.sv] - Blame information for rev 29

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 29 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
module
29
  axi4_lite_register_file
30
  #(
31
    A   = 32,     //  address bus width, must be 32 or greater for axi lite
32
    N   = 8,      //  data bus width in bytes, must be 4 or 8 for axi lite
33
    I   = 1       //  ID width
34
  )
35
  (
36
    axi4_if               axi4_s,
37
    axi4_lite_register_if r_if,
38
    input                 aclk,
39
    input                 aresetn
40
  );
41
 
42
  // --------------------------------------------------------------------
43
  //
44
  localparam LB = (N == 8) ? 3 : 2;
45
  localparam UB = LB + r_if.MW - 1;
46
 
47
 
48
  // --------------------------------------------------------------------
49
  //
50
  wire aw_rd_empty;
51
  wire w_rd_empty;
52
  wire b_wr_full;
53
  wire rf_wr_en = ~aw_rd_empty & ~w_rd_empty & ~b_wr_full;
54
  wire aw_rd_en = rf_wr_en;
55
  wire w_rd_en = rf_wr_en;
56
  wire b_wr_en = rf_wr_en;
57
 
58
  axi4_if #(.A(A), .N(N), .I(I))
59
    axi4_write_fifo(.*);
60
 
61
  axi4_to_write_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
62
    axi4_to_write_fifos_i(.*);
63
 
64
 
65
  // --------------------------------------------------------------------
66
  //
67
  wire register_select [r_if.MI-1:0];
68
  genvar j;
69
 
70
  generate
71
    for(j = 0; j < r_if.MI; j = j + 1)
72
    begin: decoder_gen
73
      assign register_select[j] = (axi4_write_fifo.awaddr[UB:LB] == j) ? 1 : 0;
74
 
75
      always_ff @(posedge aclk)
76
        if(~aresetn)
77
          r_if.register_out[j] <= 0;
78
        else if(rf_wr_en & register_select[j])
79
          r_if.register_out[j] <= axi4_write_fifo.wdata;
80
    end
81
  endgenerate
82
 
83
 
84
  // --------------------------------------------------------------------
85
  //
86
  wire ar_rd_empty;
87
  wire r_wr_full;
88
  wire rf_rd_en = ~ar_rd_empty & ~r_wr_full;
89
  wire ar_rd_en = rf_rd_en;
90
  wire r_wr_en = rf_rd_en;
91
 
92
  axi4_if #(.A(A), .N(N), .I(I))
93
    axi4_read_fifo(.*);
94
 
95
  axi4_to_read_fifos #(.A(A), .N(N), .I(I), .USE_ADVANCED_PROTOCOL(0))
96
    axi4_to_read_fifos_i(.*);
97
 
98
 
99
  // --------------------------------------------------------------------
100
  //
101
  recursive_mux #(.A(r_if.MW), .W(N*8))
102
    recursive_mux_i
103
    (
104
      .select(axi4_read_fifo.araddr[UB:LB]),
105
      .data_in(r_if.register_in),
106
      .data_out(axi4_read_fifo.rdata)
107
    );
108
 
109
 
110
  // --------------------------------------------------------------------
111
  //
112
  assign axi4_read_fifo.rid   = 0;
113
  assign axi4_read_fifo.rlast = 1;
114
  assign axi4_read_fifo.rresp = 0;
115
 
116
 
117
  // --------------------------------------------------------------------
118
  //
119
  assign axi4_write_fifo.bid   = 0;
120
  assign axi4_write_fifo.bresp = 0;
121
 
122
 
123
// --------------------------------------------------------------------
124
//
125
 
126
endmodule
127
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.