OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [sim/] [tests/] [legacy/] [tb_recursive_axis_mux/] [tb_recursive_axis_mux.sv] - Blame information for rev 50

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 50 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
// ----------------------------------------------------------------------------
28
 
29
 
30
module tb_top();
31
 
32
  // --------------------------------------------------------------------
33
  // test bench clock & reset
34
  wire clk_100mhz;
35
  wire tb_clk   = clk_100mhz;
36
  wire tb_rst;
37
 
38
  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
39
 
40
 
41
  // --------------------------------------------------------------------
42
  //
43
  wire tb_rst_s;
44
  wire aclk     = tb_clk;
45
  wire aresetn  = ~tb_rst_s;
46
  wire clk      = tb_clk;
47
  wire reset    = tb_rst_s;
48
 
49
  sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);
50
 
51
 
52
  // --------------------------------------------------------------------
53
  //
54
  import tb_recursive_axis_mux_pkg::*;
55
 
56
 
57
  // --------------------------------------------------------------------
58
  //
59
  axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in[MD-1:0](.*);
60
  axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_out(.*);
61
 
62
 
63
  // --------------------------------------------------------------------
64
  //
65
  wire [MA-1:0] select = 0;
66
 
67
  recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA))
68
    dut(.*);
69
 
70
 
71
  // --------------------------------------------------------------------
72
  // sim models
73
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
74
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
75
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
76
 
77
 
78
  // --------------------------------------------------------------------
79
  //
80
  initial
81
    axis_out.cb_s.tready <= 1;
82
 
83
 
84
  // --------------------------------------------------------------------
85
  //
86
  tb_recursive_axis_mux_class a_h;
87
 
88
  initial
89
    a_h = new(axis_in, axis_out);
90
 
91
 
92
 
93
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
94
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
95
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
96
  // sim models
97
  // --------------------------------------------------------------------
98
 
99
 
100
  // --------------------------------------------------------------------
101
  //  debug wires
102
 
103
 
104
  // --------------------------------------------------------------------
105
  // test
106
  the_test test(tb_clk, tb_rst);
107
 
108
  initial
109
    begin
110
 
111
      test.run_the_test();
112
 
113
      $display("^^^---------------------------------");
114
      $display("^^^ %16.t | Testbench done.", $time);
115
      $display("^^^---------------------------------");
116
 
117
      $display("^^^---------------------------------");
118
 
119
      $stop();
120
 
121
    end
122
 
123
endmodule
124
 
125
 
126
 

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.