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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [sim/] [tests/] [tb_axis_to_axi4_basic_dma/] [tb_axis_to_axi4_basic_dma.sv] - Blame information for rev 31

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1 31 qaztronic
// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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module tb_top();
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  // --------------------------------------------------------------------
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  // test bench clock & reset
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  wire clk_200mhz;
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  wire tb_clk   = clk_200mhz;
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  wire tb_rst;
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  tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);
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  // --------------------------------------------------------------------
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  //
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  wire tb_rst_s;
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  wire aclk     = tb_clk;
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  wire aresetn  = ~tb_rst_s;
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  sync_reset
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    sync_reset_i(aclk, tb_rst, tb_rst_s);
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  // --------------------------------------------------------------------
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  //
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  import tb_axis_to_axi4_basic_dma_pkg::*;
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  // --------------------------------------------------------------------
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  //
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  axi4_if #(.A(A), .N(N), .I(I)) axi4_m(.*);
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  axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_in(.*);
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  // --------------------------------------------------------------------
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  //
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  logic dma_enable = 0;
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  axis_to_axi4_basic_dma
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    #(
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      .A(A),
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      .N(N),
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      .I(I),
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      .BASE_ADDRESS(BASE_ADDRESS),
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      .BUFFER_SIZE(BUFFER_SIZE),
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      .BURST_LENGTH(BURST_LENGTH),
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      .MAX_BURSTS(MAX_BURSTS),
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      .BYTES_PER_TUSER(BYTES_PER_TUSER)
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    )
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    dut(.*);
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  // --------------------------------------------------------------------
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  // sim models
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  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
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  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
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  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
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  // --------------------------------------------------------------------
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  //
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  axi4_checker #(.A(A), .N(N), .MAXWAITS(64))
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    axi4_checker_i(.axi4_in(axi4_m));
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  // --------------------------------------------------------------------
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  //
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  axis_checker #(.N(N), .I(I), .D(D), .U(U), .MAXWAITS(64))
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    axis_checker_i(.axis_in(axis_in));
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  // --------------------------------------------------------------------
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  //
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  tb_axis_to_axi4_basic_dma_class a_h;
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  initial
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    a_h = new(axi4_m, axis_in);
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  // --------------------------------------------------------------------
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  //
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  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
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  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
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  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
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  // sim models
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  // --------------------------------------------------------------------
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  // --------------------------------------------------------------------
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  //  debug wires
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  // --------------------------------------------------------------------
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  // test
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  the_test test(tb_clk, tb_rst);
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  initial
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    begin
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      test.run_the_test();
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      $display("^^^---------------------------------");
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      $display("^^^ %16.t | Testbench done.", $time);
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      $display("^^^---------------------------------");
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      $display("^^^---------------------------------");
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      $stop();
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    end
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endmodule

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