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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_mux.sv] - Blame information for rev 35

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1 28 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axis_mux
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  #(
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    N,              // data bus width in bytes
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    I = 0,          // TID width
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    D = 0,          // TDEST width
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    U = 1,          // TUSER width
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    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
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    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
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  )
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  (
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    input   mux_select,
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    axis_if axis_0_in,
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    axis_if axis_1_in,
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    axis_if axis_out,
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    input   axis_en,
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    input   aclk,
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    input   aresetn
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  );
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// --------------------------------------------------------------------
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// synthesis translate_off
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  initial
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  begin
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    a_tid_unsuported:   assert(I == 0) else $fatal;
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    a_tdest_unsuported: assert(D == 0) else $fatal;
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  end
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// synthesis translate_on
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// --------------------------------------------------------------------
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  // --------------------------------------------------------------------
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  //
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  axis_if #(.N(N), .I(1), .D(1), .U(U))
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    axis_mux_out(.*);
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  assign axis_0_in.tready = mux_select ? 0                    : axis_mux_out.tready;
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  assign axis_1_in.tready = mux_select ? axis_mux_out.tready  : 0;
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  assign axis_mux_out.tvalid = mux_select ? axis_1_in.tvalid : axis_0_in.tvalid;
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  assign axis_mux_out.tdata  = mux_select ? axis_1_in.tdata  : axis_0_in.tdata;
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  assign axis_mux_out.tstrb  = mux_select ? axis_1_in.tstrb  : axis_0_in.tstrb;
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  assign axis_mux_out.tkeep  = mux_select ? axis_1_in.tkeep  : axis_0_in.tkeep;
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  assign axis_mux_out.tlast  = mux_select ? axis_1_in.tlast  : axis_0_in.tlast;
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  assign axis_mux_out.tid    = mux_select ? axis_1_in.tid    : axis_0_in.tid;
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  assign axis_mux_out.tdest  = mux_select ? axis_1_in.tdest  : axis_0_in.tdest;
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  assign axis_mux_out.tuser  = mux_select ? axis_1_in.tuser  : axis_0_in.tuser;
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  // --------------------------------------------------------------------
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  //
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  axis_register_slice
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    #(
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      .N(N),
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      .I(I),
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      .D(D),
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      .U(U),
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      .USE_TSTRB(USE_TSTRB),
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      .USE_TKEEP(USE_TKEEP)
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    )
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    axis_register_slice_i
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    (
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      .axis_in(axis_mux_out), //  .slave
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      .axis_out(axis_out),    //  .master
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      .*
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    );
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  // --------------------------------------------------------------------
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  //
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endmodule
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