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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_register_slice.sv] - Blame information for rev 36

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axis_register_slice
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  #(
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    N,              // data bus width in bytes
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    I = 1,          // TID width
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    D = 1,          // TDEST width
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    U = 1,          // TUSER width
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    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
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    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
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  )
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  (
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    axis_if axis_in,
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    axis_if axis_out,
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    input   aclk,
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    input   aresetn
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  );
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  // --------------------------------------------------------------------
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  //
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  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
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  // --------------------------------------------------------------------
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  //
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  wire          wr_full;
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  wire [W-1:0]  wr_data;
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  wire          wr_en;
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  wire          rd_empty;
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  wire [W-1:0]  rd_data;
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  wire          rd_en;
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  defparam tiny_sync_fifo_i.W=W; // why are needed these for recursive modules?
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  tiny_sync_fifo
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  // tiny_sync_fifo #(W)
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    tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);
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  // --------------------------------------------------------------------
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  //
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  generate
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    begin: assign_gen
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      if(USE_TSTRB & USE_TKEEP)
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      begin
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        assign wr_data =
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          {
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            axis_in.tdata,
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            axis_in.tlast,
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            axis_in.tuser,
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            axis_in.tstrb,
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            axis_in.tkeep
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          };
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        assign
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          {
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            axis_out.tdata,
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            axis_out.tlast,
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            axis_out.tuser,
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            axis_out.tstrb,
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            axis_out.tkeep
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          } = rd_data;
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      end
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      else if(USE_TSTRB)
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      begin
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        assign wr_data =
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          {
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            axis_in.tdata,
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            axis_in.tlast,
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            axis_in.tuser,
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            axis_in.tstrb
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          };
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        assign
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          {
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            axis_out.tdata,
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            axis_out.tlast,
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            axis_out.tuser,
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            axis_out.tstrb
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          } = rd_data;
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      end
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      else if(USE_TKEEP)
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      begin
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        assign wr_data =
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          {
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            axis_in.tdata,
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            axis_in.tlast,
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            axis_in.tuser,
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            axis_in.tkeep
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          };
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        assign
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          {
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            axis_out.tdata,
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            axis_out.tlast,
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            axis_out.tuser,
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            axis_out.tkeep
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          } = rd_data;
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      end
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      else
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      begin
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        assign wr_data =
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          {
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            axis_in.tdata,
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            axis_in.tlast,
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            axis_in.tuser
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          };
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        assign
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          {
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            axis_out.tdata,
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            axis_out.tlast,
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            axis_out.tuser
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          } = rd_data;
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      end
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  //
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  assign axis_in.tready   = ~wr_full;
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  assign wr_en            = axis_in.tvalid & ~wr_full;
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  assign axis_out.tvalid  = ~rd_empty;
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  assign rd_en            = axis_out.tready & ~rd_empty;
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// --------------------------------------------------------------------
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//
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endmodule
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