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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_register_slice.sv] - Blame information for rev 36

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module
  axis_register_slice
  #(
    N,              // data bus width in bytes
    I = 1,          // TID width
    D = 1,          // TDEST width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
  )
  (
    axis_if axis_in,
    axis_if axis_out,
    input   aclk,
    input   aresetn
  );
 
  // --------------------------------------------------------------------
  //
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
 
 
  // --------------------------------------------------------------------
  //
  wire          wr_full;
  wire [W-1:0]  wr_data;
  wire          wr_en;
 
  wire          rd_empty;
  wire [W-1:0]  rd_data;
  wire          rd_en;
 
  defparam tiny_sync_fifo_i.W=W; // why are needed these for recursive modules?
  tiny_sync_fifo
  // tiny_sync_fifo #(W)
    tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);
 
 
  // --------------------------------------------------------------------
  //
  generate
    begin: assign_gen
      if(USE_TSTRB & USE_TKEEP)
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tstrb,
            axis_in.tkeep
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tstrb,
            axis_out.tkeep
          } = rd_data;
      end
      else if(USE_TSTRB)
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tstrb
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tstrb
          } = rd_data;
      end
      else if(USE_TKEEP)
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tkeep
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tkeep
          } = rd_data;
      end
      else
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser
          } = rd_data;
      end
    end
  endgenerate
 
 
  // --------------------------------------------------------------------
  //
  assign axis_in.tready   = ~wr_full;
  assign wr_en            = axis_in.tvalid & ~wr_full;
  assign axis_out.tvalid  = ~rd_empty;
  assign rd_en            = axis_out.tready & ~rd_empty;
 
 
// --------------------------------------------------------------------
//
endmodule
 

Line No.	Rev	Author	Line
1	28	qaztronic	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Copyright (C) 2015 Authors and OPENCORES.ORG ////`
4			`//// ////`
5			`//// This source file may be used and distributed without ////`
6			`//// restriction provided that this copyright statement is not ////`
7			`//// removed from the file and that any derivative work contains ////`
8			`//// the original copyright notice and the associated disclaimer. ////`
9			`//// ////`
10			`//// This source file is free software; you can redistribute it ////`
11			`//// and/or modify it under the terms of the GNU Lesser General ////`
12			`//// Public License as published by the Free Software Foundation; ////`
13			`//// either version 2.1 of the License, or (at your option) any ////`
14			`//// later version. ////`
15			`//// ////`
16			`//// This source is distributed in the hope that it will be ////`
17			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
18			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
19			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
20			`//// details. ////`
21			`//// ////`
22			`//// You should have received a copy of the GNU Lesser General ////`
23			`//// Public License along with this source; if not, download it ////`
24			`//// from http://www.opencores.org/lgpl.shtml ////`
25			`//// ////`
26			`//////////////////////////////////////////////////////////////////////`
27
28			`module`
29			`axis_register_slice`
30			`#(`
31	36	qaztronic	`N, // data bus width in bytes`
32			`I = 1, // TID width`
33			`D = 1, // TDEST width`
34	28	qaztronic	`U = 1, // TUSER width`
35			`USE_TSTRB = 0, // set to 1 to enable, 0 to disable`
36			`USE_TKEEP = 0 // set to 1 to enable, 0 to disable`
37			`)`
38			`(`
39	31	qaztronic	`axis_if axis_in,`
40			`axis_if axis_out,`
41			`input aclk,`
42			`input aresetn`
43	28	qaztronic	`);`
44
45			`// --------------------------------------------------------------------`
46			`//`
47			`localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;`
48
49
50			`// --------------------------------------------------------------------`
51			`//`
52	31	qaztronic	`wire wr_full;`
53			`wire [W-1:0] wr_data;`
54			`wire wr_en;`
55	28	qaztronic
56	31	qaztronic	`wire rd_empty;`
57			`wire [W-1:0] rd_data;`
58			`wire rd_en;`
59	28	qaztronic
60	36	qaztronic	`defparam tiny_sync_fifo_i.W=W; // why are needed these for recursive modules?`
61			`tiny_sync_fifo`
62			`// tiny_sync_fifo #(W)`
63	31	qaztronic	`tiny_sync_fifo_i(.clk(aclk), .reset(~aresetn), .*);`
64	28	qaztronic
65	31	qaztronic
66	28	qaztronic	`// --------------------------------------------------------------------`
67			`//`
68			`generate`
69			`begin: assign_gen`
70			`if(USE_TSTRB & USE_TKEEP)`
71			`begin`
72	31	qaztronic	`assign wr_data =`
73	28	qaztronic	`{`
74			`axis_in.tdata,`
75			`axis_in.tlast,`
76			`axis_in.tuser,`
77			`axis_in.tstrb,`
78			`axis_in.tkeep`
79			`};`
80			`assign`
81			`{`
82			`axis_out.tdata,`
83			`axis_out.tlast,`
84			`axis_out.tuser,`
85			`axis_out.tstrb,`
86			`axis_out.tkeep`
87	31	qaztronic	`} = rd_data;`
88	28	qaztronic	`end`
89			`else if(USE_TSTRB)`
90			`begin`
91	31	qaztronic	`assign wr_data =`
92	28	qaztronic	`{`
93			`axis_in.tdata,`
94			`axis_in.tlast,`
95			`axis_in.tuser,`
96			`axis_in.tstrb`
97			`};`
98			`assign`
99			`{`
100			`axis_out.tdata,`
101			`axis_out.tlast,`
102			`axis_out.tuser,`
103			`axis_out.tstrb`
104	31	qaztronic	`} = rd_data;`
105	28	qaztronic	`end`
106			`else if(USE_TKEEP)`
107			`begin`
108	31	qaztronic	`assign wr_data =`
109	28	qaztronic	`{`
110			`axis_in.tdata,`
111			`axis_in.tlast,`
112			`axis_in.tuser,`
113			`axis_in.tkeep`
114			`};`
115			`assign`
116			`{`
117			`axis_out.tdata,`
118			`axis_out.tlast,`
119			`axis_out.tuser,`
120			`axis_out.tkeep`
121	31	qaztronic	`} = rd_data;`
122	28	qaztronic	`end`
123			`else`
124			`begin`
125	31	qaztronic	`assign wr_data =`
126	28	qaztronic	`{`
127			`axis_in.tdata,`
128			`axis_in.tlast,`
129			`axis_in.tuser`
130			`};`
131			`assign`
132			`{`
133			`axis_out.tdata,`
134			`axis_out.tlast,`
135			`axis_out.tuser`
136	31	qaztronic	`} = rd_data;`
137	28	qaztronic	`end`
138			`end`
139			`endgenerate`
140
141
142			`// --------------------------------------------------------------------`
143			`//`
144	31	qaztronic	`assign axis_in.tready = ~wr_full;`
145			`assign wr_en = axis_in.tvalid & ~wr_full;`
146			`assign axis_out.tvalid = ~rd_empty;`
147			`assign rd_en = axis_out.tready & ~rd_empty;`
148	28	qaztronic
149
150	31	qaztronic	`// --------------------------------------------------------------------`
151			`//`
152	28	qaztronic	`endmodule`
153

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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_register_slice.sv] - Blame information for rev 36