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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
module
  axis_synchronizer
  #(
    N = 8,          // data bus width in bytes
    I = 0,          // TID width
    D = 0,          // TDEST width
    U = 1,          // TUSER width
    USE_TSTRB = 0,  //  set to 1 to enable, 0 to disable
    USE_TKEEP = 0   //  set to 1 to enable, 0 to disable
  )
  (
    axis_if axis_in,
    axis_if axis_out,
    input   wr_clk,
    input   wr_reset,
    input   aclk,
    input   aresetn
  );
 
// --------------------------------------------------------------------
// synthesis translate_off
  initial
  begin
    a_tid_unsuported:   assert(I == 0) else $fatal;
    a_tdest_unsuported: assert(D == 0) else $fatal;
  end
// synthesis translate_on
// --------------------------------------------------------------------
 
 
  // --------------------------------------------------------------------
  //
  localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;
 
 
  // --------------------------------------------------------------------
  //
  wire          wr_full;
  wire [W-1:0]  wr_data;
  wire          wr_en;
 
  wire          rd_empty;
  wire [W-1:0]  rd_data;
  wire          rd_en;
 
  tiny_async_fifo #(.W(W))
    tiny_async_fifo_i(.rd_clk(aclk), .rd_reset(~aresetn), .*);
 
 
  // --------------------------------------------------------------------
  //
  generate
    begin: assign_gen
      if(USE_TSTRB & USE_TKEEP)
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tstrb,
            axis_in.tkeep
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tstrb,
            axis_out.tkeep
          } = rd_data;
      end
      else if(USE_TSTRB)
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tstrb
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tstrb
          } = rd_data;
      end
      else if(USE_TKEEP)
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser,
            axis_in.tkeep
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser,
            axis_out.tkeep
          } = rd_data;
      end
      else
      begin
        assign wr_data =
          {
            axis_in.tdata,
            axis_in.tlast,
            axis_in.tuser
          };
        assign
          {
            axis_out.tdata,
            axis_out.tlast,
            axis_out.tuser
          } = rd_data;
      end
    end
  endgenerate
 
 
  // --------------------------------------------------------------------
  //
  assign axis_in.tready   = ~wr_full;
  assign wr_en            = axis_in.tvalid & axis_in.tready;
  assign axis_out.tvalid  = ~rd_empty;
  assign rd_en            = axis_out.tvalid & axis_out.tready;
 
 
// --------------------------------------------------------------------
//
endmodule
 

Line No.	Rev	Author	Line
1	31	qaztronic	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Copyright (C) 2015 Authors and OPENCORES.ORG ////`
4			`//// ////`
5			`//// This source file may be used and distributed without ////`
6			`//// restriction provided that this copyright statement is not ////`
7			`//// removed from the file and that any derivative work contains ////`
8			`//// the original copyright notice and the associated disclaimer. ////`
9			`//// ////`
10			`//// This source file is free software; you can redistribute it ////`
11			`//// and/or modify it under the terms of the GNU Lesser General ////`
12			`//// Public License as published by the Free Software Foundation; ////`
13			`//// either version 2.1 of the License, or (at your option) any ////`
14			`//// later version. ////`
15			`//// ////`
16			`//// This source is distributed in the hope that it will be ////`
17			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
18			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
19			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
20			`//// details. ////`
21			`//// ////`
22			`//// You should have received a copy of the GNU Lesser General ////`
23			`//// Public License along with this source; if not, download it ////`
24			`//// from http://www.opencores.org/lgpl.shtml ////`
25			`//// ////`
26			`//////////////////////////////////////////////////////////////////////`
27
28			`module`
29			`axis_synchronizer`
30			`#(`
31			`N = 8, // data bus width in bytes`
32			`I = 0, // TID width`
33			`D = 0, // TDEST width`
34			`U = 1, // TUSER width`
35			`USE_TSTRB = 0, // set to 1 to enable, 0 to disable`
36			`USE_TKEEP = 0 // set to 1 to enable, 0 to disable`
37			`)`
38			`(`
39			`axis_if axis_in,`
40			`axis_if axis_out,`
41			`input wr_clk,`
42			`input wr_reset,`
43			`input aclk,`
44			`input aresetn`
45			`);`
46
47			`// --------------------------------------------------------------------`
48			`// synthesis translate_off`
49			`initial`
50			`begin`
51			`a_tid_unsuported: assert(I == 0) else $fatal;`
52			`a_tdest_unsuported: assert(D == 0) else $fatal;`
53			`end`
54			`// synthesis translate_on`
55			`// --------------------------------------------------------------------`
56
57
58			`// --------------------------------------------------------------------`
59			`//`
60			`localparam W = (N * 8) + (N * USE_TSTRB) + (N * USE_TKEEP) + I + D + U + 1;`
61
62
63			`// --------------------------------------------------------------------`
64			`//`
65			`wire wr_full;`
66			`wire [W-1:0] wr_data;`
67			`wire wr_en;`
68
69			`wire rd_empty;`
70			`wire [W-1:0] rd_data;`
71			`wire rd_en;`
72
73			`tiny_async_fifo #(.W(W))`
74			`tiny_async_fifo_i(.rd_clk(aclk), .rd_reset(~aresetn), .*);`
75
76
77			`// --------------------------------------------------------------------`
78			`//`
79			`generate`
80			`begin: assign_gen`
81			`if(USE_TSTRB & USE_TKEEP)`
82			`begin`
83			`assign wr_data =`
84			`{`
85			`axis_in.tdata,`
86			`axis_in.tlast,`
87			`axis_in.tuser,`
88			`axis_in.tstrb,`
89			`axis_in.tkeep`
90			`};`
91			`assign`
92			`{`
93			`axis_out.tdata,`
94			`axis_out.tlast,`
95			`axis_out.tuser,`
96			`axis_out.tstrb,`
97			`axis_out.tkeep`
98			`} = rd_data;`
99			`end`
100			`else if(USE_TSTRB)`
101			`begin`
102			`assign wr_data =`
103			`{`
104			`axis_in.tdata,`
105			`axis_in.tlast,`
106			`axis_in.tuser,`
107			`axis_in.tstrb`
108			`};`
109			`assign`
110			`{`
111			`axis_out.tdata,`
112			`axis_out.tlast,`
113			`axis_out.tuser,`
114			`axis_out.tstrb`
115			`} = rd_data;`
116			`end`
117			`else if(USE_TKEEP)`
118			`begin`
119			`assign wr_data =`
120			`{`
121			`axis_in.tdata,`
122			`axis_in.tlast,`
123			`axis_in.tuser,`
124			`axis_in.tkeep`
125			`};`
126			`assign`
127			`{`
128			`axis_out.tdata,`
129			`axis_out.tlast,`
130			`axis_out.tuser,`
131			`axis_out.tkeep`
132			`} = rd_data;`
133			`end`
134			`else`
135			`begin`
136			`assign wr_data =`
137			`{`
138			`axis_in.tdata,`
139			`axis_in.tlast,`
140			`axis_in.tuser`
141			`};`
142			`assign`
143			`{`
144			`axis_out.tdata,`
145			`axis_out.tlast,`
146			`axis_out.tuser`
147			`} = rd_data;`
148			`end`
149			`end`
150			`endgenerate`
151
152
153			`// --------------------------------------------------------------------`
154			`//`
155			`assign axis_in.tready = ~wr_full;`
156			`assign wr_en = axis_in.tvalid & axis_in.tready;`
157			`assign axis_out.tvalid = ~rd_empty;`
158			`assign rd_en = axis_out.tvalid & axis_out.tready;`
159
160
161			`// --------------------------------------------------------------------`
162			`//`
163			`endmodule`
164

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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_synchronizer.sv] - Blame information for rev 31