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1 34 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axis_test_patern
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  #(
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    N, // data bus width in bytes
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    W, // word width in bytes
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    WPB // number of words per beat
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  )
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  (
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    axis_if axis_out,
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    input   aclk,
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    input   aresetn
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  );
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// --------------------------------------------------------------------
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// synthesis translate_off
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  initial
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  begin
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    a_words_per_beat:  assert(N == W * WPB) else $fatal;
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    a_wpb: assert((WPB != 0) & ((WPB & (WPB - 1)) == 0)) else $fatal; // power of two
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  end
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// synthesis translate_on
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// --------------------------------------------------------------------
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  // --------------------------------------------------------------------
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  //
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  localparam W_LG = $clog2(W);
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  // --------------------------------------------------------------------
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  //
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  reg [(W*8)-W_LG-1:0] counter;
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  always_ff @(posedge aclk)
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    if(~aresetn)
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      counter <= 0;
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    else if(axis_out.tready & axis_out.tvalid)
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      counter <= counter + 1;
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  // --------------------------------------------------------------------
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  //  counter test pattern
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  wire [(N*8)-1:0] tp_counter;
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  genvar j;
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  generate
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    for(j = 0; j < WPB; j++)
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    begin: counting_test_pattern_gen
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      wire [W_LG-1:0] index = j;
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      assign tp_counter[j*W*8 +: W*8] = {counter, index};
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  //
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  wire [(N*8)-1:0] tp_mux_out = tp_counter;
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  // --------------------------------------------------------------------
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  //
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  assign axis_out.tvalid = 1;
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  assign axis_out.tdata = tp_mux_out;
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// --------------------------------------------------------------------
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//
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endmodule
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