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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_to_axi4_basic_dma.sv] - Blame information for rev 31

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1 31 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axis_to_axi4_basic_dma
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  #(
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    A, // address bus width
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    N, // data bus width in bytes
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    I, // ID width
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    BASE_ADDRESS,       // must be on 4K boundry
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    BUFFER_SIZE,
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    BURST_LENGTH,
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    MAX_BURSTS,
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    BYTES_PER_TUSER = 0 //  bytes per tuser bit. Set to 0 for transfer based.
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  )
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  (
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    axi4_if axi4_m,
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    axis_if axis_in,    // tuser[0] indicates first words of buffer. The rest of tuser is not used.
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    input   dma_enable,
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    input   aclk,
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    input   aresetn
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  );
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  // --------------------------------------------------------------------
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  //
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  localparam W_D = BURST_LENGTH * MAX_BURSTS;
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  localparam AW_D = 2;
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  localparam WATERMARK = BURST_LENGTH;
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  localparam STRIDE = N * BURST_LENGTH;
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  localparam ADDRESS_END = BASE_ADDRESS + BUFFER_SIZE;
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  localparam ADDRESS_STOP = (ADDRESS_END % STRIDE == 0) ? ADDRESS_END : ADDRESS_END + STRIDE;
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  // localparam U = N / BYTES_PER_TUSER;
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// --------------------------------------------------------------------
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// synthesis translate_off
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  localparam N_4K = 'h1000 / 'h8; // number of bytes in 4K
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  initial
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  begin
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    a_4k_mod_base_address: assert(BASE_ADDRESS % 'h1000 == 0) else $fatal;
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    a_4k_gt_eq_stride: assert(N_4K >= STRIDE) else $fatal;
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    a_4k_mod_stride: assert('h1000 % STRIDE == 0) else $fatal;
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    a_burst_length: assert(BURST_LENGTH > 1) else $fatal;
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    // a_bytes_per_tuser: assert(N % BYTES_PER_TUSER == 0) else $fatal;
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  end
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// synthesis translate_on
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// --------------------------------------------------------------------
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  // --------------------------------------------------------------------
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  //
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  axi4_if #(.A(A), .N(N), .I(I))  axi4_write_fifo(.*);
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  // --------------------------------------------------------------------
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  //
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  wire axis_data_en = axis_in.tready  & axis_in.tvalid;
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  wire start        = axis_data_en    & axis_in.tuser[0];
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  // --------------------------------------------------------------------
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  //
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  reg [(A-1):0] awaddr_r;
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  wire send_waddr;
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  wire awaddr_en = (awaddr_r < ADDRESS_STOP);
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  wire aw_wr_full;
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  wire aw_wr_en = ~aw_wr_full & dma_enable & awaddr_en & send_waddr;
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  wire w_wr_full;
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  wire w_wr_en = axis_in.tready & axis_in.tvalid;
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  wire w_topped_off;
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  wire w_watermark;
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  wire b_rd_empty;
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  wire b_rd_en = ~b_rd_empty;
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  // --------------------------------------------------------------------
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  //
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  reg [$clog2(W_D + 1):0] w_wr_counter;
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  wire burst_ready = (w_wr_counter > BURST_LENGTH - 1);
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  wire wlast = (w_wr_counter == BURST_LENGTH - 1);
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  always_ff @(posedge aclk)
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    if(~aresetn)
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      w_wr_counter <= 0;
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    else if(aw_wr_en)
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      if(w_wr_en)
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        w_wr_counter <= w_wr_counter - BURST_LENGTH + 1;
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      else
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        w_wr_counter <= w_wr_counter - BURST_LENGTH;
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    else if(w_wr_en)
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      w_wr_counter <= w_wr_counter + 1;
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  // --------------------------------------------------------------------
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  //
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  // reg [$clog2(AW_D + 1):0] aw_wr_counter;
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  // assign send_waddr = (aw_wr_counter > 0);
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  assign send_waddr = burst_ready;
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  // always_ff @(posedge aclk)
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    // if(~aresetn)
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      // aw_wr_counter <= 0;
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    // else if(aw_wr_en & ~burst_ready)
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      // aw_wr_counter <= aw_wr_counter - 1;
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    // else if(~aw_wr_en & burst_ready)
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      // aw_wr_counter <= aw_wr_counter + 1;
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  // --------------------------------------------------------------------
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  //
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  always_ff @(posedge aclk)
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    if(~aresetn | ~awaddr_en | start)
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      awaddr_r <= BASE_ADDRESS;
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    else if(aw_wr_en)
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      awaddr_r <= awaddr_r + STRIDE;
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  // --------------------------------------------------------------------
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  //
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  axi4_m_to_write_fifos
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    #(
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      .A(A),
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      .N(N),
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      .I(I),
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      .W_D(W_D),
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      .B_D(AW_D),
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      .AW_D(AW_D),
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      .WATERMARK(WATERMARK)
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    )
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    axi4_m_to_write_fifos_i(.*);
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  // --------------------------------------------------------------------
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  //
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  assign axi4_write_fifo.awaddr    = awaddr_r;
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  assign axi4_write_fifo.awid      = 0;
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  assign axi4_write_fifo.awburst   = 2'b01;
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  assign axi4_write_fifo.awsize    = $clog2(N);
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  assign axi4_write_fifo.awlen     = BURST_LENGTH - 1;
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  // --------------------------------------------------------------------
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  //
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  assign axi4_write_fifo.wdata  = axis_in.tdata;
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  assign axi4_write_fifo.wid    = 0;
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  assign axi4_write_fifo.wlast  = wlast;
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  assign axi4_write_fifo.wstrb  = {N{1'b1}};
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  // --------------------------------------------------------------------
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  //
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  assign axis_in.tready = ~w_wr_full & ~burst_ready;
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  // --------------------------------------------------------------------
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  //
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  assign axi4_m.arvalid   = 0;
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  assign axi4_m.rready    = 0;
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  assign axi4_m.awcache   = 0;
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  assign axi4_m.awlock    = 0;
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  assign axi4_m.awprot    = 0;
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  assign axi4_m.awqos     = 0;
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  assign axi4_m.awregion  = 0;
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// --------------------------------------------------------------------
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//
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endmodule
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