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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [axis_to_memory.sv] - Blame information for rev 50

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1 50 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axis_to_memory
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  #(
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    W, // data width in bits
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    A, // address width in bits
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    P = 1 // pipeline delay
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  )
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  (
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    axis_if        axis_ar,
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    axis_if        axis_r,
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    output         wr,
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    output [A-1:0] addr,
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    output [W-1:0] din,
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    input  [W-1:0] dout,
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    input          aclk,
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    input          aresetn
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  );
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  // --------------------------------------------------------------------
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  localparam CW = ($clog2(P) == 0) ? 1 : $clog2(P);
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  localparam D = 2 ** CW;
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  localparam UB = $clog2(D);
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  // --------------------------------------------------------------------
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  reg [P-1:0] pipeline;
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  wire ar = axis_ar.tready & axis_ar.tvalid;
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  wire rd_ready = pipeline[0];
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  wire bypass;
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  generate
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    if(P > 1) begin: pipeline_gen
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      always_ff @(posedge aclk)
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        if(~aresetn)
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          pipeline <= 0;
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        else
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          pipeline <= {ar, pipeline[P-1:1]};
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    end
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    else begin: min_pipeline_gen // P == 1
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      always_ff @(posedge aclk)
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        if(~aresetn)
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          pipeline <= 0;
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        else
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          pipeline <= ar;
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    end
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  endgenerate
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  // --------------------------------------------------------------------
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  wire          wr_full;
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  wire [W-1:0]  wr_data = dout;
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  wire          wr_en = bypass ? 0 : rd_ready;
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  wire          rd_empty;
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  wire [W-1:0]  rd_data;
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  wire          rd_en = axis_r.tready & axis_r.tvalid & ~bypass;
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  wire [UB:0]   count;
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  sync_fifo #(W, D) fifo_i(.clk(aclk), .reset(~aresetn), .*);
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  // --------------------------------------------------------------------
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  // assign bypass = rd_empty & (count != 0) & rd_ready;
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  assign bypass = 0;
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  // // --------------------------------------------------------------------
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  // logic [$clog2($bits(pipeline)+1)-1:0] in_pipeline;
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  // always_comb begin
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    // in_pipeline = '0;
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    // foreach(pipeline[idx]) begin
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      // in_pipeline += pipeline[idx];
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    // end
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  // end
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  // --------------------------------------------------------------------
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  reg [$clog2($bits(pipeline)+1)-1:0] pipeline_count;
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  reg [$clog2($bits(pipeline)+1)-1:0] next_pipeline_count;
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  always_comb
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    case({rd_ready, ar})
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      2'b0_0: next_pipeline_count = pipeline_count;
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      2'b0_1: next_pipeline_count = pipeline_count + 1;
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      2'b1_0: next_pipeline_count = pipeline_count - 1;
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      2'b1_1: next_pipeline_count = pipeline_count;
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  endcase
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  always_ff @(posedge aclk)
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    if(~aresetn)
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      pipeline_count <= 0;
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    else
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      pipeline_count <= next_pipeline_count;
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  // --------------------------------------------------------------------
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  assign axis_ar.tready = (pipeline_count + count < D) | rd_en;
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  assign axis_r.tdata = bypass ? dout : rd_data;
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  assign axis_r.tlast = 1;
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  assign axis_r.tvalid = ~rd_empty | bypass;
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  // --------------------------------------------------------------------
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  assign wr = 0;
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  // assign addr = axis_ar.tdata;
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// --------------------------------------------------------------------
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endmodule

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