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[/] [qaz_libs/] [trunk/] [axi4_stream_lib/] [src/] [recursive_axis_catenate.sv] - Blame information for rev 36

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1 36 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  recursive_axis_catenate
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  #(
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    N, // data bus width in bytes
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    I = 1, // TID width
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    D = 1, // TDEST width
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    U = 1, // TUSER width
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    U_IS_EOP = -1,
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    MA, // mux select width
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    MD = 2 ** MA
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  )
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  (
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    axis_if         axis_in [MD-1:0],
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    axis_if         axis_out,
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    input           aclk,
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    input           aresetn
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  );
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  // --------------------------------------------------------------------
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  //
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  generate
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    if(MA == 1)
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    begin: catenate_gen
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      axis_catenate #(.N(N), .I(I), .D(D), .U(U), .U_IS_EOP(U_IS_EOP))
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        axis_catenate_i(.*);
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    end
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    else
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    begin: recursive_catenate_gen
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      // --------------------------------------------------------------------
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      //
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      axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_catenate_out[1:0](.*);
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      recursive_axis_catenate
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        #(
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          .N(N),
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          .I(I),
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          .D(D),
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          .U(U),
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          .U_IS_EOP(U_IS_EOP),
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          .MA(MA - 1)
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        )
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        catenate_lo
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        (
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          .axis_in(axis_in[(MD/2)-1:0]),
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          .axis_out(axis_catenate_out[0]),
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          .*
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        );
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      // --------------------------------------------------------------------
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      //
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      recursive_axis_catenate
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        #(
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          .N(N),
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          .I(I),
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          .D(D),
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          .U(U),
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          .U_IS_EOP(U_IS_EOP),
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          .MA(MA - 1)
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        )
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        catenate_hi
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        (
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          .axis_in(axis_in[MD-1:(MD/2)]),
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          .axis_out(axis_catenate_out[1]),
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          .*
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        );
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      // --------------------------------------------------------------------
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      //
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      axis_catenate
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        #(
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          .N(N),
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          .I(I),
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          .D(D),
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          .U(U),
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          .U_IS_EOP(U_IS_EOP)
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        )
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        axis_catenate_i(.axis_in(axis_catenate_out), .*);
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    end
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  endgenerate
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// --------------------------------------------------------------------
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//
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endmodule
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