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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////

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//////////////////////////////////////////////////////////////////////

module

  recursive_axis_mux

  #(

    N, // data bus width in bytes

    I = 1, // TID width

    D = 1, // TDEST width

    U = 1, // TUSER width

    MA, // mux select width

    MD = 2 ** MA

  )

  (

    input [MA-1:0]  select,

    axis_if         axis_in [MD-1:0],

    axis_if         axis_out,

    input           aclk,

    input           aresetn

  );

  // --------------------------------------------------------------------

  //

  generate

    if(MA == 1)

    begin: mux_gen

      axis_mux #(.N(N), .I(I), .D(D), .U(U))

        axis_mux_i(.*);

    end

    else

    begin: recurse_mux_gen

      axis_if #(.N(N), .I(I), .D(D), .U(U)) axis_mux_out[1:0](.*);

      recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA - 1))

        mux_lo

        (

          .select(select[MA-2:0]),

          .axis_in(axis_in[(MD/2)-1:0]),

          .axis_out(axis_mux_out[0]),

          .*

        );

      recursive_axis_mux #(.N(N), .I(I), .D(D), .U(U), .MA(MA - 1))

        mux_hi

        (

          .select(select[MA-2:0]),

          .axis_in(axis_in[MD-1:(MD/2)]),

          .axis_out(axis_mux_out[1]),

          .*

        );

      axis_mux #(.N(N), .I(I), .D(D), .U(U))

        axis_mux_i

        (

          .select(select[MA-1]),

          .axis_in(axis_mux_out),

          .*

        );

    end

  endgenerate

// --------------------------------------------------------------------

//

endmodule