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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_PRBS-7/] [prbs_7_testbench.v] - Blame information for rev 34

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1 34 qaztronic
// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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`timescale 10ps/1ps
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module
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  prbs_7_testbench();
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  // --------------------------------------------------------------------
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  reg clock = 0;
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  always
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    #(20) clock <= ~clock;
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  // --------------------------------------------------------------------
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  reg reset = 1;
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  initial
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    begin
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      reset <= 1'b1;
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      repeat(3)
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        @(posedge clock);
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      reset <= 1'b0;
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    end
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  // --------------------------------------------------------------------
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  wire [7:0] prbs_7_to_8_data_out;
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  prbs_7_to_8 i_prbs_7_to_8
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  (
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    .data_in( 8'h0 ),
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    .scram_en( 1'b1 ),
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    .scram_rst( reset ),
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    .data_out(prbs_7_to_8_data_out),
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    .rst( reset ),
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    .clk( clock )
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  );
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  // --------------------------------------------------------------------
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  wire [13:0] prbs_7_to_14_data_out;
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  prbs_7_to_14 i_prbs_7_to_14
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  (
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    .data_in( 14'h0 ),
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    .scram_en( 1'b1 ),
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    .scram_rst( reset ),
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    .data_out(prbs_7_to_14_data_out),
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    .rst( reset ),
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    .clk( clock )
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  );
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  // --------------------------------------------------------------------
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  //  LFSR pseudo-random  x^7 + x^6 + 1  
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  reg [7:0] lfsr;
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  wire      lfsr_feedback = lfsr[6] ^ lfsr[5];
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  always @(posedge clock)
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    if( reset )
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      lfsr <= 8'hff;
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    else
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      lfsr <= {lfsr[6:0], lfsr_feedback};
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  // --------------------------------------------------------------------
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  integer i = 0;
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  integer fh;
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  initial
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    begin
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      fh = $fopen( "prbs_7.csv" );
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      $fdisplay( fh, "count, parallel 8 bit, parallel 14 bit, serial" );
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    end
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  always @( posedge clock )
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    begin
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      if( ~reset )
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        begin
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          $display( "-#- %16.t | 0x%2x | 0x%4x | 0x%2x", $time, prbs_7_to_8_data_out, prbs_7_to_14_data_out, lfsr );
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          $fdisplay( fh, "%d,'%2x,'%4x,'%2x", i, prbs_7_to_8_data_out, prbs_7_to_14_data_out, lfsr );
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          i = i + 1;
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        end
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    end
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endmodule
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