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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_fifo/] [fifo_monitor.svh] - Blame information for rev 44

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1 44 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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class fifo_monitor extends uvm_component;
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  `uvm_component_utils(fifo_monitor);
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  virtual fifo_if #(.W(W), .D(D)) vif;
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  uvm_analysis_port #(fifo_sequence_item) ap;
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  // --------------------------------------------------------------------
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  function new (string name, uvm_component parent);
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    super.new(name,parent);
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  endfunction
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  // --------------------------------------------------------------------
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  function void build_phase(uvm_phase phase);
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    ap = new("ap", this);
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  endfunction : build_phase
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  // --------------------------------------------------------------------
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  task run_phase(uvm_phase phase);
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    fifo_sequence_item item;
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    fifo_sequence_item c_item;
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    item = fifo_sequence_item::type_id::create("item");
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    forever @(vif.cb iff vif.cb.reset === 0)
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      if(vif.cb.wr_en || vif.cb.rd_en)
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      begin
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        $cast(c_item, item.clone);
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        c_item.wr_full = vif.cb.wr_full;
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        c_item.wr_data = vif.cb.wr_data;
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        c_item.rd_empty = vif.cb.rd_empty;
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        c_item.rd_data = vif.cb.rd_data;
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        c_item.count = vif.cb.count;
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        if(vif.cb.wr_en && vif.cb.rd_en)
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          c_item.command = FIFO_BOTH;
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        else if(vif.cb.wr_en)
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          c_item.command = FIFO_WR;
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        else if(vif.cb.rd_en)
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          c_item.command = FIFO_RD;
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        ap.write(c_item);
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      end
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  endtask : run_phase
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// --------------------------------------------------------------------
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endclass : fifo_monitor

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