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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_fifo/] [tb_top.sv] - Blame information for rev 44

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1 44 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2018 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module tb_top;
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  import uvm_pkg::*;
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  import tb_fifo_pkg::*;
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  `include "uvm_macros.svh"
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  // --------------------------------------------------------------------
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  wire clk_100mhz;
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  wire tb_clk = clk_100mhz;
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  wire tb_rst;
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  wire clk_1000mhz;
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  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
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  // --------------------------------------------------------------------
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  wire clk = clk_100mhz;
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  wire reset = tb_rst;
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  // --------------------------------------------------------------------
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  fifo_if #(.W(W), .D(D)) dut_if(.*);
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  sync_fifo #(.W(W), .D(D))
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    dut
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    (
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      .wr_full(dut_if.wr_full),
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      .wr_data(dut_if.wr_data),
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      .wr_en(dut_if.wr_en),
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      .rd_empty(dut_if.rd_empty),
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      .rd_data(dut_if.rd_data),
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      .rd_en(dut_if.rd_en),
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      .count(dut_if.count),
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      .clk(dut_if.clk),
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      .reset(dut_if.reset)
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    );
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  // --------------------------------------------------------------------
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  tb_dut_config #(.W(W), .D(D)) cfg_h = new(dut_if);
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  initial
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  begin
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    uvm_config_db #(tb_dut_config #(.W(W), .D(D)))::set(null, "*", "tb_dut_config", cfg_h);
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    run_test("t_debug");
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  end
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// --------------------------------------------------------------------
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endmodule

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