OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_gear_box/] [tb_top.v] - Blame information for rev 34

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 34 qaztronic
// --------------------------------------------------------------------
2
//
3
// --------------------------------------------------------------------
4
 
5
`timescale 10ps/1ps
6
 
7
 
8
module tb_top();
9
 
10
  // --------------------------------------------------------------------
11
  // system wires
12
  wire  clk_250;
13
 
14
  wire tb_clk = clk_250;
15
 
16
  wire tb_rst;
17
 
18
 
19
  // --------------------------------------------------------------------
20
  // clock & reset
21
 
22
  parameter CLK_PERIOD = 400; // use 250MHZ for main clk
23
 
24
  tb_clk #( .CLK_PERIOD(400) ) i_clk_250   ( clk_250 );
25
 
26
  tb_reset #( .ASSERT_TIME(CLK_PERIOD*10) ) i_tb_rst( tb_rst );
27
 
28
  initial
29
    begin
30
      $display("\n^^^---------------------------------");
31
      #(CLK_PERIOD/3);
32
      i_tb_rst.assert_reset();
33
    end
34
 
35
 
36
  // dut
37
  // --------------------------------------------------------------------
38
  wire          ugb_adc_rd_en;
39
 
40
  wire          fifo_full;
41
  wire          fifo_empty;
42
  reg   [12:0]  fifo_wr_data;
43
  wire  [12:0]  fifo_rd_data;
44
  wire          fifo_wr_en = ~tb_rst & ~fifo_full;
45
  wire          fifo_rd_en = ~tb_rst & ugb_adc_rd_en & ~fifo_empty;
46
 
47
  wire  [12:0]  ugb_adc_bus = fifo_rd_data;
48
  wire  [7:0]   ugb_out;
49
 
50
  unbuffered_gear_box
51
    i_unbuffered_gear_box
52
    (
53
    .adc_bus(ugb_adc_bus),
54
    .adc_rd_en(ugb_adc_rd_en),
55
 
56
    .out(ugb_out),
57
 
58
    .gb_en(~fifo_empty),
59
    .clk_250(clk_250),
60
    .sys_reset(tb_rst)
61
    );
62
 
63
sync_fifo
64
  i_sync_fifo
65
  (
66
    .fifo_wr_data(fifo_wr_data),
67
    .fifo_rd_data(fifo_rd_data),
68
    .fifo_wr_en(fifo_wr_en),
69
    .fifo_rd_en(fifo_rd_en),
70
 
71
    .fifo_full(fifo_full),
72
    .fifo_empty(fifo_empty),
73
 
74
    .fifo_clock(clk_250),
75
    .fifo_reset(tb_rst)
76
  );
77
 
78
 
79
  // --------------------------------------------------------------------
80
  // dut
81
 
82
 
83
  // --------------------------------------------------------------------
84
  // sim modles
85
 
86
//  tb_log log();
87
 
88
 
89
  always @( posedge clk_250 )
90
    if( tb_rst )
91
      fifo_wr_data <= 0;
92
    else if( fifo_wr_en )
93
      fifo_wr_data <= fifo_wr_data + 1;
94
 
95
  reg [103:0] ugb_out_r;
96
 
97
  always @( posedge clk_250 )
98
    ugb_out_r <= {ugb_out, ugb_out_r[103:8]};
99
 
100
 
101
  wire [12:0] dbg_ugb_shift[7:0];
102
 
103
  assign dbg_ugb_shift[0] = ugb_out_r[12:0];
104
  assign dbg_ugb_shift[1] = ugb_out_r[25:13];
105
  assign dbg_ugb_shift[2] = ugb_out_r[38:26];
106
  assign dbg_ugb_shift[3] = ugb_out_r[51:39];
107
  assign dbg_ugb_shift[4] = ugb_out_r[64:52];
108
  assign dbg_ugb_shift[5] = ugb_out_r[77:65];
109
  assign dbg_ugb_shift[6] = ugb_out_r[90:78];
110
  assign dbg_ugb_shift[7] = ugb_out_r[103:91];
111
 
112
  wire [7:0] dbg_ugb_out[12:0];
113
 
114
  assign dbg_ugb_out[0]  = ugb_out_r[7:0];
115
  assign dbg_ugb_out[1]  = ugb_out_r[15:8];
116
  assign dbg_ugb_out[2]  = ugb_out_r[23:16];
117
  assign dbg_ugb_out[3]  = ugb_out_r[31:24];
118
  assign dbg_ugb_out[4]  = ugb_out_r[39:32];
119
  assign dbg_ugb_out[5]  = ugb_out_r[47:40];
120
  assign dbg_ugb_out[6]  = ugb_out_r[55:48];
121
  assign dbg_ugb_out[7]  = ugb_out_r[63:56];
122
  assign dbg_ugb_out[8]  = ugb_out_r[71:64];
123
  assign dbg_ugb_out[9]  = ugb_out_r[79:72];
124
  assign dbg_ugb_out[10] = ugb_out_r[87:80];
125
  assign dbg_ugb_out[11] = ugb_out_r[95:88];
126
  assign dbg_ugb_out[12] = ugb_out_r[103:96];
127
 
128
  reg [12:0] dbg_ugb_pixels_out_r[7:0];
129
  integer   j;
130
 
131
  always @( posedge clk_250 )
132
    if( i_unbuffered_gear_box.gear_select == 0 )
133
      for( j = 0; j < 8; j = j + 1 )
134
        dbg_ugb_pixels_out_r[j] <= dbg_ugb_shift[j];
135
 
136
 
137
  // sim modles
138
  // --------------------------------------------------------------------
139
 
140
 
141
  // --------------------------------------------------------------------
142
  // waveform signals
143
  wire [3:0] gear = i_unbuffered_gear_box.gear_select;
144
  wire bank_sel = i_unbuffered_gear_box.adc_bus_bank_select;
145
  wire [12:0] adc_bus_in = ugb_adc_bus;
146
  wire [7:0] gear_box_out = ugb_out;
147
  wire adc_bus_rd_en = ugb_adc_rd_en;
148
 
149
 
150
  // --------------------------------------------------------------------
151
  // test
152
  the_test test( tb_clk, tb_rst );
153
 
154
  initial
155
    begin
156
 
157
      wait( ~tb_rst );
158
 
159
      repeat(2) @(posedge tb_clk);
160
 
161
      test.run_the_test();
162
 
163
      $display("\n^^^---------------------------------");
164
      $display("^^^ %15.t | Testbench done.\n", $time);
165
      $display("\n^^^---------------------------------");
166
 
167
//      log.log_fail_count();
168
      $display("\n^^^---------------------------------");
169
 
170
`ifdef DEBUG
171
      $stop();
172
`else
173
      $finish();
174
`endif
175
 
176
    end
177
 
178
endmodule
179
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.