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[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_gear_box/] [tb_top.v] - Blame information for rev 34

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1 34 qaztronic
// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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`timescale 10ps/1ps
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module tb_top();
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  // --------------------------------------------------------------------
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  // system wires
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  wire  clk_250;
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  wire tb_clk = clk_250;
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  wire tb_rst;
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  // --------------------------------------------------------------------
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  // clock & reset
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  parameter CLK_PERIOD = 400; // use 250MHZ for main clk
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  tb_clk #( .CLK_PERIOD(400) ) i_clk_250   ( clk_250 );
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  tb_reset #( .ASSERT_TIME(CLK_PERIOD*10) ) i_tb_rst( tb_rst );
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  initial
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    begin
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      $display("\n^^^---------------------------------");
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      #(CLK_PERIOD/3);
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      i_tb_rst.assert_reset();
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    end
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  // dut
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  // --------------------------------------------------------------------
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  wire          ugb_adc_rd_en;
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  wire          fifo_full;
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  wire          fifo_empty;
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  reg   [12:0]  fifo_wr_data;
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  wire  [12:0]  fifo_rd_data;
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  wire          fifo_wr_en = ~tb_rst & ~fifo_full;
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  wire          fifo_rd_en = ~tb_rst & ugb_adc_rd_en & ~fifo_empty;
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  wire  [12:0]  ugb_adc_bus = fifo_rd_data;
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  wire  [7:0]   ugb_out;
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  unbuffered_gear_box
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    i_unbuffered_gear_box
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    (
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    .adc_bus(ugb_adc_bus),
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    .adc_rd_en(ugb_adc_rd_en),
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    .out(ugb_out),
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    .gb_en(~fifo_empty),
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    .clk_250(clk_250),
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    .sys_reset(tb_rst)
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    );
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sync_fifo
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  i_sync_fifo
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  (
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    .fifo_wr_data(fifo_wr_data),
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    .fifo_rd_data(fifo_rd_data),
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    .fifo_wr_en(fifo_wr_en),
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    .fifo_rd_en(fifo_rd_en),
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    .fifo_full(fifo_full),
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    .fifo_empty(fifo_empty),
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    .fifo_clock(clk_250),
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    .fifo_reset(tb_rst)
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  );
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  // --------------------------------------------------------------------
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  // dut
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  // --------------------------------------------------------------------
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  // sim modles
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//  tb_log log();
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  always @( posedge clk_250 )
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    if( tb_rst )
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      fifo_wr_data <= 0;
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    else if( fifo_wr_en )
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      fifo_wr_data <= fifo_wr_data + 1;
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  reg [103:0] ugb_out_r;
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  always @( posedge clk_250 )
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    ugb_out_r <= {ugb_out, ugb_out_r[103:8]};
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  wire [12:0] dbg_ugb_shift[7:0];
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  assign dbg_ugb_shift[0] = ugb_out_r[12:0];
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  assign dbg_ugb_shift[1] = ugb_out_r[25:13];
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  assign dbg_ugb_shift[2] = ugb_out_r[38:26];
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  assign dbg_ugb_shift[3] = ugb_out_r[51:39];
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  assign dbg_ugb_shift[4] = ugb_out_r[64:52];
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  assign dbg_ugb_shift[5] = ugb_out_r[77:65];
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  assign dbg_ugb_shift[6] = ugb_out_r[90:78];
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  assign dbg_ugb_shift[7] = ugb_out_r[103:91];
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  wire [7:0] dbg_ugb_out[12:0];
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  assign dbg_ugb_out[0]  = ugb_out_r[7:0];
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  assign dbg_ugb_out[1]  = ugb_out_r[15:8];
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  assign dbg_ugb_out[2]  = ugb_out_r[23:16];
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  assign dbg_ugb_out[3]  = ugb_out_r[31:24];
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  assign dbg_ugb_out[4]  = ugb_out_r[39:32];
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  assign dbg_ugb_out[5]  = ugb_out_r[47:40];
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  assign dbg_ugb_out[6]  = ugb_out_r[55:48];
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  assign dbg_ugb_out[7]  = ugb_out_r[63:56];
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  assign dbg_ugb_out[8]  = ugb_out_r[71:64];
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  assign dbg_ugb_out[9]  = ugb_out_r[79:72];
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  assign dbg_ugb_out[10] = ugb_out_r[87:80];
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  assign dbg_ugb_out[11] = ugb_out_r[95:88];
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  assign dbg_ugb_out[12] = ugb_out_r[103:96];
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  reg [12:0] dbg_ugb_pixels_out_r[7:0];
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  integer   j;
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  always @( posedge clk_250 )
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    if( i_unbuffered_gear_box.gear_select == 0 )
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      for( j = 0; j < 8; j = j + 1 )
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        dbg_ugb_pixels_out_r[j] <= dbg_ugb_shift[j];
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  // sim modles
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  // --------------------------------------------------------------------
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  // --------------------------------------------------------------------
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  // waveform signals
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  wire [3:0] gear = i_unbuffered_gear_box.gear_select;
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  wire bank_sel = i_unbuffered_gear_box.adc_bus_bank_select;
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  wire [12:0] adc_bus_in = ugb_adc_bus;
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  wire [7:0] gear_box_out = ugb_out;
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  wire adc_bus_rd_en = ugb_adc_rd_en;
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  // --------------------------------------------------------------------
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  // test
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  the_test test( tb_clk, tb_rst );
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  initial
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    begin
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      wait( ~tb_rst );
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      repeat(2) @(posedge tb_clk);
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      test.run_the_test();
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      $display("\n^^^---------------------------------");
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      $display("^^^ %15.t | Testbench done.\n", $time);
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      $display("\n^^^---------------------------------");
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//      log.log_fail_count();
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      $display("\n^^^---------------------------------");
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`ifdef DEBUG
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      $stop();
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`else
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      $finish();
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`endif
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    end
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endmodule
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