OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [basal/] [sim/] [tests/] [tb_one_hot_encoder/] [tb_one_hot_encoder.sv] - Blame information for rev 34

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 34 qaztronic
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
4
////                                                              ////
5
//// This source file may be used and distributed without         ////
6
//// restriction provided that this copyright statement is not    ////
7
//// removed from the file and that any derivative work contains  ////
8
//// the original copyright notice and the associated disclaimer. ////
9
////                                                              ////
10
//// This source file is free software; you can redistribute it   ////
11
//// and/or modify it under the terms of the GNU Lesser General   ////
12
//// Public License as published by the Free Software Foundation; ////
13
//// either version 2.1 of the License, or (at your option) any   ////
14
//// later version.                                               ////
15
////                                                              ////
16
//// This source is distributed in the hope that it will be       ////
17
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
18
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
19
//// PURPOSE.  See the GNU Lesser General Public License for more ////
20
//// details.                                                     ////
21
////                                                              ////
22
//// You should have received a copy of the GNU Lesser General    ////
23
//// Public License along with this source; if not, download it   ////
24
//// from http://www.opencores.org/lgpl.shtml                     ////
25
////                                                              ////
26
//////////////////////////////////////////////////////////////////////
27
 
28
`timescale 1ps/1ps
29
 
30
 
31
module tb_top();
32
 
33
  // --------------------------------------------------------------------
34
  // test bench clock & reset
35
  wire clk_200mhz;
36
  wire tb_clk   = clk_200mhz;
37
  wire tb_rst;
38
 
39
  tb_base #(.PERIOD(5_000)) tb(clk_200mhz, tb_rst);
40
 
41
 
42
  // --------------------------------------------------------------------
43
  //
44
  localparam A = 5;  // encoder select width
45
  localparam D = 2 ** A;
46
 
47
 
48
  // --------------------------------------------------------------------
49
  //
50
  reg [A-1:0] select = 0;
51
  wire [D-1:0] encoded;
52
 
53
  one_hot_encoder #(A)
54
    dut(.*);
55
 
56
 
57
  // --------------------------------------------------------------------
58
  // sim models
59
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
60
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
61
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
62
 
63
 
64
 
65
  // --------------------------------------------------------------------
66
  //
67
 
68
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
69
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
70
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
71
  // sim models
72
  // --------------------------------------------------------------------
73
 
74
 
75
  // --------------------------------------------------------------------
76
  //  debug wires
77
 
78
 
79
  // --------------------------------------------------------------------
80
  // test
81
  initial
82
    begin
83
 
84
      // --------------------------------------------------------------------
85
      wait(~tb_rst)
86
      #50ns;
87
 
88
      repeat(D + 1)
89
        @(posedge tb_clk)
90
          select++;
91
 
92
 
93
      // --------------------------------------------------------------------
94
      #50ns;
95
 
96
      $display("^^^---------------------------------");
97
      $display("^^^ %16.t | Testbench done.", $time);
98
      $display("^^^---------------------------------");
99
 
100
      $display("^^^---------------------------------");
101
 
102
      $stop();
103
 
104
    end
105
 
106
endmodule
107
 
108
 
109
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.