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[/] [qaz_libs/] [trunk/] [basal/] [src/] [FIFOs/] [async_fifo.sv] - Blame information for rev 49

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1 38 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2016 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// --------------------------------------------------------------------
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//
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module
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  cummings_sync_r2w
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  #(
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    parameter ADDRSIZE = 4
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  )
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  (
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    output reg [ADDRSIZE:0] wq2_rptr,
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    input [ADDRSIZE:0]      rptr,
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    input                   wclk,
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    input                   wrst_n
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  );
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  reg [ADDRSIZE:0] wq1_rptr;
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  always @(posedge wclk or negedge wrst_n)
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    if (!wrst_n)
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      {wq2_rptr,wq1_rptr} <= 0;
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    else
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      {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
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endmodule
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// --------------------------------------------------------------------
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//
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module
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  cummings_sync_w2r
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  #(
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    parameter ADDRSIZE = 4
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  )
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  (
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    output reg  [ADDRSIZE:0]  rq2_wptr,
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    input       [ADDRSIZE:0]  wptr,
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    input                     rclk,
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    input                     rrst_n
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  );
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  reg [ADDRSIZE:0] rq1_wptr;
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70
  always @(posedge rclk or negedge rrst_n)
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    if(!rrst_n)
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      {rq2_wptr,rq1_wptr} <= 0;
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    else
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      {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
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endmodule
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// --------------------------------------------------------------------
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//
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module
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  cummings_fifomem
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  #(
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    parameter DATASIZE = 8,   // Memory data word width
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    parameter ADDRSIZE = 4    // Number of mem address bits
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  )
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  (
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    output [DATASIZE-1:0] rdata,
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    input [DATASIZE-1:0]  wdata,
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    input [ADDRSIZE-1:0]  waddr,
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    input [ADDRSIZE-1:0]  raddr,
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    input wclken,
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    input wfull,
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    input wclk
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  );
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97
  // RTL Verilog memory model
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  localparam DEPTH = 1<
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  reg [DATASIZE-1:0] mem [0:DEPTH-1];
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  assign rdata = mem[raddr];
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102
  always @(posedge wclk)
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    if(wclken && !wfull)
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      mem[waddr] <= wdata;
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106
endmodule
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// --------------------------------------------------------------------
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//
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module
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  cummings_rptr_empty
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  #(
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    parameter ADDRSIZE = 4
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  )
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  (
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    output reg                  rempty,
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    output      [ADDRSIZE-1:0]  raddr,
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    output reg  [ADDRSIZE :0]   rptr,
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    input       [ADDRSIZE :0]   rq2_wptr,
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    input                       rinc,
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    input                       rclk,
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    input                       rrst_n
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  );
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126
  reg [ADDRSIZE:0] rbin;
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  wire [ADDRSIZE:0] rgraynext, rbinnext;
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  //-------------------
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  // GRAYSTYLE2 pointer
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  //-------------------
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  always @(posedge rclk or negedge rrst_n)
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    if(!rrst_n)
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      {rbin, rptr} <= 0;
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    else
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      {rbin, rptr} <= {rbinnext, rgraynext};
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  // Memory read-address pointer (okay to use binary to address memory)
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  assign raddr = rbin[ADDRSIZE-1:0];
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  assign rbinnext = rbin + (rinc & ~rempty);
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  assign rgraynext = (rbinnext>>1) ^ rbinnext;
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  //---------------------------------------------------------------
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  // FIFO empty when the next rptr == synchronized wptr or on reset
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  //---------------------------------------------------------------
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  assign rempty_val = (rgraynext == rq2_wptr);
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148
  always @(posedge rclk or negedge rrst_n)
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    if(!rrst_n)
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      rempty <= 1'b1;
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    else
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      rempty <= rempty_val;
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154
endmodule
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// --------------------------------------------------------------------
158
//
159
module
160
  cummings_wptr_full
161
  #(
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    parameter ADDRSIZE = 4
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  )
164
  (
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    output reg                  wfull,
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    output      [ADDRSIZE-1:0]  waddr,
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    output reg  [ADDRSIZE :0]   wptr,
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    input       [ADDRSIZE :0]   wq2_rptr,
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    input                       winc,
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    input                       wclk,
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    input                       wrst_n
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  );
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  reg [ADDRSIZE:0] wbin;
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  wire [ADDRSIZE:0] wgraynext, wbinnext;
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  // GRAYSTYLE2 pointer
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  always @(posedge wclk or negedge wrst_n)
179
    if(!wrst_n)
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      {wbin, wptr} <= 0;
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    else
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      {wbin, wptr} <= {wbinnext, wgraynext};
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  // Memory write-address pointer (okay to use binary to address memory)
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  assign waddr = wbin[ADDRSIZE-1:0];
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  assign wbinnext = wbin + (winc & ~wfull);
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  assign wgraynext = (wbinnext>>1) ^ wbinnext;
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  //------------------------------------------------------------------
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  // Simplified version of the three necessary full-tests:
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  // assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
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  // (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
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  // (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
194
  //------------------------------------------------------------------
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  assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1], wq2_rptr[ADDRSIZE-2:0]});
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197
  always @(posedge wclk or negedge wrst_n)
198
    if(!wrst_n)
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      wfull <= 1'b0;
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    else
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      wfull <= wfull_val;
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203
endmodule
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// --------------------------------------------------------------------
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//
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module
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  cummings_fifo1
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  #(
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    parameter DSIZE = 8,
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    parameter ASIZE = 4
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  )
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  (
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    output [DSIZE-1:0]  rdata,
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    output              wfull,
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    output              rempty,
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    input [DSIZE-1:0]   wdata,
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    input               winc,
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    input               wclk,
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    input               wrst_n,
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    input               rinc,
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    input               rclk,
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    input               rrst_n
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  );
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  wire [ASIZE-1:0] waddr, raddr;
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  wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
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  cummings_sync_r2w sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr),
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  .wclk(wclk), .wrst_n(wrst_n));
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  cummings_sync_w2r sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr),
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  .rclk(rclk), .rrst_n(rrst_n));
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  cummings_fifomem #(DSIZE, ASIZE) fifomem
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  (.rdata(rdata), .wdata(wdata),
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  .waddr(waddr), .raddr(raddr),
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  .wclken(winc), .wfull(wfull),
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  .wclk(wclk));
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  cummings_rptr_empty #(ASIZE) rptr_empty
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  (.rempty(rempty),
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  .raddr(raddr),
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  .rptr(rptr), .rq2_wptr(rq2_wptr),
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  .rinc(rinc), .rclk(rclk),
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  .rrst_n(rrst_n));
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  cummings_wptr_full #(ASIZE) wptr_full
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  (.wfull(wfull), .waddr(waddr),
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  .wptr(wptr), .wq2_rptr(wq2_rptr),
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  .winc(winc), .wclk(wclk),
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  .wrst_n(wrst_n));
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endmodule
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// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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265
module
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  async_fifo
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  #(
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    W,
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    D
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  )
271
  (
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    output            wr_full,
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    input  [W-1:0]    wr_data,
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    input             wr_en,
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    input             wr_clk,
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    input             wr_reset,
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278
    output            rd_empty,
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    output  [W-1:0]   rd_data,
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    input             rd_en,
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    input             rd_clk,
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    input             rd_reset
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  );
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285
  // --------------------------------------------------------------------
286
  //
287
  cummings_fifo1 #(.DSIZE(W), .ASIZE($clog2(D)))
288
    cummings_fifo1_i
289
    (
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      .rdata(rd_data),
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      .wfull(wr_full),
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      .rempty(rd_empty),
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      .wdata(wr_data),
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      .winc(wr_en),
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      .wclk(wr_clk),
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      .wrst_n(~wr_reset),
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      .rinc(rd_en),
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      .rclk(rd_clk),
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      .rrst_n(~rd_reset)
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    );
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302
 
303
// --------------------------------------------------------------------
304
// synthesis translate_off
305
  always_ff @(posedge wr_clk)
306
    if(wr_en & wr_full)
307
      $stop;
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  always_ff @(posedge rd_clk)
309
    if(rd_en & rd_empty)
310
      $stop;
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// synthesis translate_on
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// --------------------------------------------------------------------
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314
 
315
// --------------------------------------------------------------------
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//
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endmodule
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