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[/] [qaz_libs/] [trunk/] [basal/] [src/] [FIFOs/] [bc_sync_fifo.v] - Blame information for rev 34

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// -*- mode: Verilog; verilog-auto-lineup-declaration: nil; -*-
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//-----------------------------------------------------------------------------
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// Title         : Synchronous FIFO
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// Project       : Common
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//-----------------------------------------------------------------------------
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// File          : sync_fifo.v
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//-----------------------------------------------------------------------------
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// Description : Synchronous FIFO using BRAM.
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//
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// Implements a variable width/depth synchronous FIFO. The synthesis
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// tool may choose to implement the memory as a block RAM.
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//-----------------------------------------------------------------------------
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// Copyright 1994-2009 Beyond Circuits. All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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//   1. Redistributions of source code must retain the above copyright notice, 
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//      this list of conditions and the following disclaimer.
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//   2. Redistributions in binary form must reproduce the above copyright notice, 
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//      this list of conditions and the following disclaimer in the documentation 
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//      and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE BEYOND CIRCUITS ``AS IS'' AND ANY EXPRESS OR 
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
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// SHALL BEYOND CIRCUITS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
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// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module bc_sync_fifo
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  #(
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    parameter depth = 32,
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    parameter width = 32,
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    // Need the log of the parameters as parameters also due to an XST bug.
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    parameter log2_depth = log2(depth),
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    parameter log2_depthp1 = log2(depth+1)
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    )
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  (
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   input clk,
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   input reset,
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   input wr_enable,
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   input rd_enable,
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   output reg empty,
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   output reg full,
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   output [width-1:0] rd_data,
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   input [width-1:0] wr_data,
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   output reg [log2_depthp1-1:0] count
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   );
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  // log2 -- return the log base 2 of value.
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  function integer log2;
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    input [31:0] value;
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    begin
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      value = value-1;
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      for (log2=0; value>0; log2=log2+1)
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        value = value>>1;
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    end
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  endfunction
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  // increment -- add one to value modulo depth.
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  function [log2_depth-1:0] increment;
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    input [log2_depth-1:0] value;
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    begin
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      if (value == depth-1)
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        increment = 0;
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      else
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        increment = value+1;
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    end
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  endfunction
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  // writing -- true when we write to the RAM.
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  wire writing = wr_enable && (rd_enable || !full);
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  // reading -- true when we are reading from the RAM.
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  wire reading = rd_enable && !empty;
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  // rd_ptr -- the read pointer.
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  reg [log2_depth-1:0] rd_ptr;
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  // next_rd_ptr -- the next value for the read pointer.
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  // We need to name this combinational value because it
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  // is needed to use the write-before-read style RAM.
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  reg [log2_depth-1:0] next_rd_ptr;
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  always @(*)
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    if (reset)
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      next_rd_ptr = 0;
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    else if (reading)
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      next_rd_ptr = increment(rd_ptr);
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    else
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      next_rd_ptr = rd_ptr;
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  always @(posedge clk)
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    rd_ptr <= next_rd_ptr;
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  // wr_ptr -- the write pointer
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  reg [log2_depth-1:0] wr_ptr;
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  // next_wr_ptr -- the next value for the write pointer.
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  reg [log2_depth-1:0] next_wr_ptr;
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  always @(*)
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    if (reset)
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      next_wr_ptr = 0;
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    else if (writing)
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      next_wr_ptr = increment(wr_ptr);
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    else
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      next_wr_ptr = wr_ptr;
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  always @(posedge clk)
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    wr_ptr <= next_wr_ptr;
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  // count -- the number of valid entries in the FIFO.
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  always @(posedge clk)
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    if (reset)
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      count <= 0;
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    else if (writing && !reading)
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      count <= count+1;
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    else if (reading && !writing)
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      count <= count-1;
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  // empty -- true if the FIFO is empty.
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  // Note that this doesn't depend on count so if the count
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  // output is unused the logic for computing the count can
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  // be optimized away.
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  always @(posedge clk)
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    if (reset)
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      empty <= 1;
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    else if (reading && next_wr_ptr == next_rd_ptr && !full)
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      empty <= 1;
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    else
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      if (writing && !reading)
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        empty <= 0;
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  // full -- true if the FIFO is full.
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  // Again, this is not dependent on count.
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  always @(posedge clk)
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    if (reset)
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      full <= 0;
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    else if (writing && next_wr_ptr == next_rd_ptr)
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      full <= 1;
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    else if (reading && !writing)
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      full <= 0;
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  // We need to infer a write first style RAM so that when 
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  // the FIFO is empty the write data can flow through to
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  // the read side and be available the next clock cycle.
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  reg [width-1:0] mem [depth-1:0];
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  always @(posedge clk)
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    if (writing)
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      mem[wr_ptr] <= wr_data;
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  assign rd_data = mem[rd_ptr];
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endmodule
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