OpenCores
URL https://opencores.org/ocsvn/qaz_libs/qaz_libs/trunk

Subversion Repositories qaz_libs

[/] [qaz_libs/] [trunk/] [basal/] [src/] [FIFOs/] [ohmkara/] [sync_fifo.v] - Blame information for rev 34

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 34 qaztronic
///////////////////////////////////////////////
2
// Author: Deepak (28/03/2009 08:54)
3
// Module: fifo.v
4
// Project:
5
// Description: Synchronous FIFO
6
//    data output (dout) is un-registered.
7
// Version: 1.1 (not icarus verilog compatible)
8
//
9
///////////////////////////////////////////////
10
 
11
module sync_fifo
12
#(
13
 parameter DATA_WIDTH = 8,
14
 parameter DEPTH = 8</pre>
15
)
16
(
17
 input [DATA_WIDTH-1:0]  din,
18
 input wr_en,
19
 input rd_en,
20
 output [DATA_WIDTH-1:0] dout,
21
 output reg full,
22
 output reg empty,
23
 
24
 input clk,
25
 input reset
26
);
27
 
28
function integer log2;
29
 input integer n;
30
 begin
31
 log2 = 0;
32
 while(2**log2 < n) begin
33
 log2=log2+1;
34
 end
35
 end
36
endfunction
37
 
38
parameter ADDR_WIDTH = log2(DEPTH);
39
reg   [ADDR_WIDTH : 0]     rd_ptr; // note MSB is not really address
40
reg   [ADDR_WIDTH : 0]     wr_ptr; // note MSB is not really address
41
wire  [ADDR_WIDTH-1 : 0]  wr_loc;
42
wire  [ADDR_WIDTH-1 : 0]  rd_loc;
43
reg   [DATA_WIDTH-1 : 0]  mem[DEPTH-1 : 0];
44
 
45
assign wr_loc = wr_ptr[ADDR_WIDTH-1 : 0];
46
assign rd_loc = rd_ptr[ADDR_WIDTH-1 : 0];
47
 
48
always @(posedge clk) begin
49
 if(reset) begin
50
 wr_ptr <= 'h0;
51
 rd_ptr <= 'h0;
52
end // end if
53
else begin
54
 if(wr_en & (~full))begin
55
 wr_ptr <= wr_ptr+1;
56
 end
57
 if(rd_en & (~empty))
58
 rd_ptr <= rd_ptr+1;
59
 end //end else
60
end//end always
61
 
62
//empty if all the bits of rd_ptr and wr_ptr are the same.
63
//full if all bits except the MSB are equal and MSB differes
64
always @(rd_ptr or wr_ptr)begin
65
 //default catch-alls
66
 empty <= 1'b0;
67
 full  <= 1'b0;
68
 if(rd_ptr[ADDR_WIDTH-1:0]==wr_ptr[ADDR_WIDTH-1:0])begin
69
 if(rd_ptr[ADDR_WIDTH]==wr_ptr[ADDR_WIDTH])
70
 empty <= 1'b1;
71
 else
72
 full  <= 1'b1;
73
 end//end if
74
end//end always
75
 
76
always @(posedge clk) begin
77
 if (wr_en)
78
 mem[wr_loc] <= din;
79
end //end always
80
 
81
//comment if you want a registered dout
82
assign dout = rd_en ? mem[rd_loc]:'h0;
83
//uncomment if you want a registered dout
84
//always @(posedge clk) begin
85
//   if (reset)
86
//      dout <= 'h0;
87
//   else if (rd_en)
88
//      dout <= mem[rd_ptr];
89
//end
90
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.