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[/] [qaz_libs/] [trunk/] [basal/] [src/] [FIFOs/] [ohmkara/] [sync_fifo.v] - Blame information for rev 34

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1 34 qaztronic
///////////////////////////////////////////////
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// Author: Deepak (28/03/2009 08:54)
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// Module: fifo.v
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// Project:
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// Description: Synchronous FIFO
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//    data output (dout) is un-registered.
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// Version: 1.1 (not icarus verilog compatible)
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//
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///////////////////////////////////////////////
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module sync_fifo
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#(
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 parameter DATA_WIDTH = 8,
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 parameter DEPTH = 8</pre>
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)
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(
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 input [DATA_WIDTH-1:0]  din,
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 input wr_en,
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 input rd_en,
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 output [DATA_WIDTH-1:0] dout,
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 output reg full,
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 output reg empty,
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 input clk,
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 input reset
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);
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function integer log2;
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 input integer n;
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 begin
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 log2 = 0;
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 while(2**log2 < n) begin
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 log2=log2+1;
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 end
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 end
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endfunction
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parameter ADDR_WIDTH = log2(DEPTH);
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reg   [ADDR_WIDTH : 0]     rd_ptr; // note MSB is not really address
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reg   [ADDR_WIDTH : 0]     wr_ptr; // note MSB is not really address
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wire  [ADDR_WIDTH-1 : 0]  wr_loc;
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wire  [ADDR_WIDTH-1 : 0]  rd_loc;
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reg   [DATA_WIDTH-1 : 0]  mem[DEPTH-1 : 0];
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assign wr_loc = wr_ptr[ADDR_WIDTH-1 : 0];
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assign rd_loc = rd_ptr[ADDR_WIDTH-1 : 0];
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always @(posedge clk) begin
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 if(reset) begin
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 wr_ptr <= 'h0;
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 rd_ptr <= 'h0;
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end // end if
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else begin
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 if(wr_en & (~full))begin
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 wr_ptr <= wr_ptr+1;
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 end
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 if(rd_en & (~empty))
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 rd_ptr <= rd_ptr+1;
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 end //end else
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end//end always
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//empty if all the bits of rd_ptr and wr_ptr are the same.
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//full if all bits except the MSB are equal and MSB differes
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always @(rd_ptr or wr_ptr)begin
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 //default catch-alls
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 empty <= 1'b0;
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 full  <= 1'b0;
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 if(rd_ptr[ADDR_WIDTH-1:0]==wr_ptr[ADDR_WIDTH-1:0])begin
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 if(rd_ptr[ADDR_WIDTH]==wr_ptr[ADDR_WIDTH])
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 empty <= 1'b1;
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 else
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 full  <= 1'b1;
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 end//end if
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end//end always
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always @(posedge clk) begin
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 if (wr_en)
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 mem[wr_loc] <= din;
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end //end always
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//comment if you want a registered dout
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assign dout = rd_en ? mem[rd_loc]:'h0;
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//uncomment if you want a registered dout
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//always @(posedge clk) begin
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//   if (reset)
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//      dout <= 'h0;
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//   else if (rd_en)
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//      dout <= mem[rd_ptr];
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//end
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endmodule

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