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[/] [qaz_libs/] [trunk/] [basal/] [src/] [FIFOs/] [sync_fifo.sv] - Blame information for rev 34

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1 34 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  sync_fifo
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  #(
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    W = 8,
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    D = 16,
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    UB = $clog2(D)
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  )
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  (
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    output            wr_full,
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    input   [W-1:0]   wr_data,
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    input             wr_en,
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    output            rd_empty,
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    output  [W-1:0]   rd_data,
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    input             rd_en,
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    output  [UB:0]    count,
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    input             clk,
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    input             reset
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  );
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  // --------------------------------------------------------------------
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  //
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  generate
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    begin: fifo_gen
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      if(D == 2)
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      begin
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        assign count = 0;
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        tiny_sync_fifo #(.W(W))
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          tiny_sync_fifo_i(.*);
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      end
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      else
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      begin
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        bc_sync_fifo #(.depth(D), .width(W))
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          bc_sync_fifo_i
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          (
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            .wr_enable(wr_en),
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            .rd_enable(rd_en),
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            .empty(rd_empty),
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            .full(wr_full),
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            .count(count),
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            .*
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           );
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      end
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    end
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  endgenerate
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// --------------------------------------------------------------------
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//
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endmodule
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