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[/] [qaz_libs/] [trunk/] [basal/] [src/] [FIFOs/] [tiny_sync_fifo.v] - Blame information for rev 43

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1 43 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  tiny_sync_fifo
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  #(
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    parameter W
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  )
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  (
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    output  reg       wr_full,
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    input   [W-1:0]   wr_data,
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    input             wr_en,
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    output  reg       rd_empty,
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    output  [W-1:0]   rd_data,
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    input             rd_en,
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    input             clk,
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    input             reset
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  );
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  // --------------------------------------------------------------------
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  //
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  wire writing = wr_en & ~wr_full;
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  wire reading = rd_en & ~rd_empty;
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  // --------------------------------------------------------------------
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  //
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  reg [1:0] rd_ptr_r;
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  reg [1:0] next_rd_ptr_r;
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  always @(*)
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    if(reset)
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      next_rd_ptr_r = 0;
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    else if(reading)
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      next_rd_ptr_r = rd_ptr_r + 1;
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    else
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      next_rd_ptr_r = rd_ptr_r;
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  always @(posedge clk)
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    rd_ptr_r <= next_rd_ptr_r;
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  // --------------------------------------------------------------------
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  //
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  reg [1:0] wr_ptr_r;
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  reg [1:0] next_wr_ptr_r;
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  always @(*)
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    if(reset)
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      next_wr_ptr_r = 0;
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    else if(writing)
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      next_wr_ptr_r = wr_ptr_r + 1;
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    else
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      next_wr_ptr_r = wr_ptr_r;
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  always @(posedge clk)
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    wr_ptr_r <= next_wr_ptr_r;
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  // --------------------------------------------------------------------
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  //
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  wire empty_w = (next_wr_ptr_r == next_rd_ptr_r);
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  always @(posedge clk)
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    if(reset)
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      rd_empty <= 1;
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    else
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      rd_empty <= empty_w;
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  // --------------------------------------------------------------------
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  //
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  wire full_w = ({~next_wr_ptr_r[1],next_wr_ptr_r[0]} == next_rd_ptr_r);
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  always @(posedge clk)
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    if(reset)
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      wr_full <= 0;
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    else
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      wr_full <= full_w;
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  // --------------------------------------------------------------------
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  //
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  reg   [W-1:0] data_0_r;
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  reg   [W-1:0] data_1_r;
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  wire  [W-1:0] wr_data_mux = rd_ptr_r[0] ? data_1_r : data_0_r;
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  assign rd_data = wr_data_mux;
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  always @(posedge clk)
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    if(writing)
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      if(wr_ptr_r[0])
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        data_1_r <= wr_data;
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      else
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        data_0_r <= wr_data;
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// --------------------------------------------------------------------
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// synthesis translate_off
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  always @(posedge clk)
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    if(wr_en & wr_full)
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      $stop;
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  always @(posedge clk)
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    if(rd_en & rd_empty)
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      $stop;
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// synthesis translate_on
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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endmodule

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