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[/] [qaz_libs/] [trunk/] [basal/] [src/] [RAM/] [asym_ram_sdp_write_wider.v] - Blame information for rev 34

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1 34 qaztronic
// Asymmetric port RAM
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// Write wider than Read. Write Statement in a loop.
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// asym_ram_sdp_write_wider.v
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module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA,
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doB);
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parameter WIDTHB = 4;
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parameter SIZEB = 1024;
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parameter ADDRWIDTHB = 10;
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parameter WIDTHA = 16;
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parameter SIZEA = 256;
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parameter ADDRWIDTHA = 8;
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input clkA;
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input clkB;
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input weA;
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input enaA, enaB;
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input [ADDRWIDTHA-1:0] addrA;
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input [ADDRWIDTHB-1:0] addrB;
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input [WIDTHA-1:0] diA;
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output [WIDTHB-1:0] doB;
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`define max(a,b) {(a) > (b) ? (a) : (b)}
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`define min(a,b) {(a) < (b) ? (a) : (b)}
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function integer log2;
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input integer value;
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reg [31:0] shifted;
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integer res;
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begin
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if (value < 2)
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log2 = value;
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else
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begin
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shifted = value-1;
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for (res=0; shifted>0; res=res+1)
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shifted = shifted>>1;
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log2 = res;
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end
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end
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endfunction
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localparam maxSIZE = `max(SIZEA, SIZEB);
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localparam maxWIDTH = `max(WIDTHA, WIDTHB);
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localparam minWIDTH = `min(WIDTHA, WIDTHB);
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localparam RATIO = maxWIDTH / minWIDTH;
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localparam log2RATIO = log2(RATIO);
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reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
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reg [WIDTHB-1:0] readB;
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always @(posedge clkB) begin
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if (enaB) begin
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readB <= RAM[addrB];
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end
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end
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assign doB = readB;
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always @(posedge clkA)
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begin : ramwrite
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integer i;
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reg [log2RATIO-1:0] lsbaddr;
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for (i=0; i< RATIO; i= i+ 1) begin : write1
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lsbaddr = i;
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if (enaA) begin
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if (weA)
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RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
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end
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end
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end
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endmodule

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