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[/] [qaz_libs/] [trunk/] [basal/] [src/] [RAM/] [bram_tdp.v] - Blame information for rev 34

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1 34 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// --------------------------------------------------------------------
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// A parameterized, inferable, true dual-port, dual-clock block RAM in Verilog.
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module
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  bram_tdp
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  #(
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    parameter W,
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    parameter A
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  )
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  (
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    // Port A
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    input               a_clk,
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    input               a_wr,
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    input       [A-1:0] a_addr,
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    input       [W-1:0] a_din,
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    output  reg [W-1:0] a_dout,
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    // Port B
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    input               b_clk,
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    input               b_wr,
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    input       [A-1:0] b_addr,
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    input       [W-1:0] b_din,
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    output  reg [W-1:0] b_dout
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  );
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  // --------------------------------------------------------------------
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  // Shared memory
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  reg [W-1:0] mem [(2**A)-1:0];
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  // --------------------------------------------------------------------
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  // Port A
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  always @(posedge a_clk)
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  begin
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      a_dout      <= mem[a_addr];
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      if(a_wr) begin
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          a_dout      <= a_din;
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          mem[a_addr] <= a_din;
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      end
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  end
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  // --------------------------------------------------------------------
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  // Port B
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  always @(posedge b_clk)
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  begin
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      b_dout      <= mem[b_addr];
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      if(b_wr) begin
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          b_dout      <= b_din;
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          mem[b_addr] <= b_din;
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      end
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  end
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// --------------------------------------------------------------------
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//
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endmodule
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