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[/] [qaz_libs/] [trunk/] [basal/] [src/] [RAM/] [byte_enabled_simple_dual_port_ram.sv] - Blame information for rev 34

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1 34 qaztronic
module byte_enabled_simple_dual_port_ram
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(
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input we, clk,
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input [5:0] waddr, raddr, // address width = 6
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input [3:0] be, // 4 bytes per word
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input [31:0] wdata, // byte width = 8, 4 bytes per word
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output reg [31:0] q // byte width = 8, 4 bytes per word
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);
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// use a multi-dimensional packed array
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//to model individual bytes within the word
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logic [3:0][7:0] ram[0:63]; // # words = 1 << address width
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always_ff@(posedge clk)
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begin
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if(we) begin
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if(be[0]) ram[waddr][0] <= wdata[7:0];
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if(be[1]) ram[waddr][1] <= wdata[15:8];
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if(be[2]) ram[waddr][2] <= wdata[23:16];
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if(be[3]) ram[waddr][3] <= wdata[31:24];
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end
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q <= ram[raddr];
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end
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endmodule

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