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[/] [qaz_libs/] [trunk/] [basal/] [src/] [ROM/] [axis_rom.sv] - Blame information for rev 49

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1 49 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  axis_rom
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  #(
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    int N,
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    int A,
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    string FILE_NAME,
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    int START=0,
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    int STOP=2**A
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  )
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  (
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    axis_if axis_out,
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    input   aclk,
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    input   aresetn
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  );
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  // --------------------------------------------------------------------
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  wire wr_full;
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  wire rd_empty;
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  wire rd_en = axis_out.tready & axis_out.tvalid;
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  // --------------------------------------------------------------------
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  enum reg [2:0]
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    {
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      INIT    = 3'b001,
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      STALLED = 3'b010,
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      PRIMED  = 3'b100
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    } state, next_state;
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  // --------------------------------------------------------------------
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  always_ff @(posedge aclk)
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    if(~aresetn)
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      state <= INIT;
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    else
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      state <= next_state;
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  // --------------------------------------------------------------------
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  always_comb
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    case(state)
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      INIT:       next_state <= STALLED;
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      STALLED:    if(~wr_full)
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                    next_state <= PRIMED;
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                  else
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                    next_state <= STALLED;
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      PRIMED:     if(rd_empty | (~wr_full & rd_en))
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                    next_state <= PRIMED;
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                  else
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                    next_state <= STALLED;
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      default:    next_state <= INIT;
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    endcase
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  // --------------------------------------------------------------------
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  wire [(N*8)-1:0]  q;
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  reg [(A-1):0] addr;
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  rom #((N*8), A, FILE_NAME) rom(.clk(aclk), .*);
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  // --------------------------------------------------------------------
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  wire [N*8:0] wr_data;
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  wire [N*8:0] rd_data;
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  wire wr_en = (state == PRIMED);
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  tiny_sync_fifo #((N*8)+1) fifo(.clk(aclk), .reset(~aresetn), .*);
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  // --------------------------------------------------------------------
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  reg increment;
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  always_comb
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    case({state, next_state})
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      {STALLED,  PRIMED}: increment <= 1;
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      {PRIMED,   PRIMED}: increment <= 1;
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      default:            increment <= 0;
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    endcase
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  // --------------------------------------------------------------------
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  wire stop = increment & (addr >= STOP - START - 1);
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  always_ff @(posedge aclk)
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    if(~aresetn | stop)
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      addr <= 0;
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    else if(increment)
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      addr <= addr + 1;
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  // --------------------------------------------------------------------
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  reg tlast;
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  always_ff @(posedge aclk)
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    if(stop)
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      tlast <= 1;
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    else if(~aresetn | wr_en)
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      tlast <= 0;
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  // --------------------------------------------------------------------
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  assign axis_out.tvalid = ~rd_empty;
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  assign {axis_out.tlast, axis_out.tdata} = rd_data;
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  assign wr_data = {tlast, q};
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// --------------------------------------------------------------------
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endmodule

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