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[/] [qaz_libs/] [trunk/] [basal/] [src/] [gear_box/] [unbuffered_gear_box.v] - Blame information for rev 34

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1 34 qaztronic
// --------------------------------------------------------------------
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//
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// --------------------------------------------------------------------
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module
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  unbuffered_gear_box(
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    input       [12:0]  adc_bus,
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    output              adc_rd_en,
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    output reg  [7:0]   out,
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    input               gb_en,
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    input               clk_250,
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    input               sys_reset
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  );
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  // --------------------------------------------------------------------
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  //
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  wire        adc_bus_bank_select;
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  wire [3:0]  gear_select;
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  wire        ugb_enable = gb_en;
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  unbuffered_gear_box_fsm
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    i_unbuffered_gear_box_fsm
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    (
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      .ugb_enable(ugb_enable),
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      .adc_bus_bank_select(adc_bus_bank_select),
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      .adc_rd_en(adc_rd_en),
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      .gear_select(gear_select),
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      .ugb_clock(clk_250),
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      .ugb_reset(sys_reset)
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    );
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  // --------------------------------------------------------------------
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  //
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  reg   [12:0] adc_bus_b0_r;
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  reg   [12:0] adc_bus_b1_r;
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  always @( posedge clk_250 )
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    if( ~adc_bus_bank_select )
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        adc_bus_b0_r <= adc_bus;
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  always @( posedge clk_250 )
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    if( adc_bus_bank_select )
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        adc_bus_b1_r <= adc_bus;
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  // --------------------------------------------------------------------
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  //  bypass mux
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  wire  [12:0] adc_bus_b0_w = adc_bus_bank_select ? adc_bus_b0_r : adc_bus;
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  wire  [12:0] adc_bus_b1_w = adc_bus_bank_select ? adc_bus : adc_bus_b1_r;
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  wire  [25:0] adc_bus_mux = {adc_bus_b1_w, adc_bus_b0_w};
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  // --------------------------------------------------------------------
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  //  out mux
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  always @( * )
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    case( gear_select )
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      4'h0:     out = adc_bus_mux[7:0];
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      4'h1:     out = adc_bus_mux[15:8];
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      4'h2:     out = adc_bus_mux[23:16];
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      4'h3:     out = {adc_bus_mux[5:0],adc_bus_mux[25:24]};
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      4'h4:     out = adc_bus_mux[13:6];
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      4'h5:     out = adc_bus_mux[21:14];
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      4'h6:     out = {adc_bus_mux[3:0],adc_bus_mux[25:22]};
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      4'h7:     out = adc_bus_mux[11:4];
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      4'h8:     out = adc_bus_mux[19:12];
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      4'h9:     out = {adc_bus_mux[1:0],adc_bus_mux[25:20]};
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      4'ha:     out = adc_bus_mux[9:2];
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      4'hb:     out = adc_bus_mux[17:10];
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      4'hc:     out = adc_bus_mux[25:18];
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      default:  out = adc_bus_mux[7:0];
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    endcase
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endmodule

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