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[/] [qaz_libs/] [trunk/] [basal/] [src/] [synchronize/] [pulse_synchronizer.v] - Blame information for rev 37

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1 37 qaztronic
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2015 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module
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  pulse_synchronizer
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  (
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    input   in,
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    output  out,
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    output  busy,
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    input   in_clk,
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    input   in_reset,
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    input   out_clk,
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    input   out_reset
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  );
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  // --------------------------------------------------------------------
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  //
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  reg [1:0] in_s;
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  reg in_r;
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  wire in_w = in ? 1 : (in_s[1] ? 0 : in_r);
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  always @(posedge in_clk)
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    if(in_reset)
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      in_r <= 0;
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    else
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      in_r <= in_w;
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  // --------------------------------------------------------------------
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  //
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  reg [2:0] out_r;
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  always @(posedge out_clk)
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    if(out_reset)
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      out_r <= 0;
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    else
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      out_r <= {out_r[1:0], in_r};
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  // --------------------------------------------------------------------
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  //  
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  always @(posedge in_clk)
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    if(in_reset)
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      in_s <= 0;
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    else
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      in_s <= {in_s[0], out_r[1]};
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  // --------------------------------------------------------------------
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  //
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  assign out = out_r[1] & ~out_r[2];
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  assign busy = in_s[1] | in_r;
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// --------------------------------------------------------------------
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//
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endmodule
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