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[/] [qaz_libs/] [trunk/] [camera_link/] [camera_link_clk.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 qaztronic
//
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//
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//
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`timescale 10ps/1ps
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module camera_link_clk
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(
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  input             clk_in,
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  output reg [3:0]  clk_7x_index,
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  output            clk_out_7x,
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  output            clock_good,
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  input             reset
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);
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  // --------------------------------------------------------------------
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  //
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  clock_mult
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    #( .MULT(7) )
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    clk_out_7x_i
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    (
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      .clock_in(clk_in),
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      .clock_out(clk_out_7x),
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      .clock_good(clock_good),
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      .reset(reset)
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    );
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  // --------------------------------------------------------------------
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  //
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  wire delayed_clk_in;
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  assign #1 delayed_clk_in = clk_in;
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  wire clk_in_rise = (delayed_clk_in == 1'b0) & (clk_in == 1'b1);
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  always @(posedge clk_out_7x)
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    begin
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      if(clk_in_rise)
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        clk_7x_index <= 5;
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      else if( clk_7x_index >= 6 )
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        clk_7x_index <= 0;
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      else
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        clk_7x_index <= clk_7x_index + 1;
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    end
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endmodule
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